Pmlimitu6 - Prefetchable Memory Limit Address Upper; Pmlimitu6 - Prefetchable Memory Limit Address Upper Register - Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
6.2.20

PMLIMITU6 - Prefetchable Memory Limit Address Upper

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Limit Address register
controls the CPU to PCI Express-G prefetchable memory access routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40- bit address. The lower 8 bits of the Upper Limit Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range is at the top of a 1-MB aligned memory block.
Note that prefetchable memory range is supported to allow segregation by the
configuration software between the memory ranges that must be defined as UC and the
ones that can be designated as a USWC (i.e., prefetchable) from the CPU perspective.
Table 43.

PMLIMITU6 - Prefetchable Memory Limit Address Upper Register

Default
Bit Access
31:0 RW 00000000h
® TM
Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
August 2010
Document Number: 323178-003
RST/
Value PWR
Core Prefetchable Memory Address Limit (MLIMITU)
Corresponds to A[63:32] of the upper limit of the prefetchable
Memory range that is passed to PCI Express-G.
0/6/0/PCI
2C-2Fh
00000000h
RW
32 bits
Description
® ®
Celeron Processor P4505, U3405 Series
Datasheet Addendum
101