Slotsts - Slot Status; Slotsts - Slot Status Register - Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
6.2.43

SLOTSTS - Slot Status

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PCI Express Slot related registers allow for the support of Hot Plug.
Table 66. SLOTSTS - Slot Status Register (Sheet 1 of 2)
Default
Bit Access
Value
15:9 RO 0000000b
8 RO
7 RO
6 RO
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Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
August 2010
Document Number: 323178-003
RST/
PWR
Core Reserved and Zero
For future R/WC/S implementations; software must use 0 for
writes to bits.
0b Core Reserved for Data Link Layer State Changed (DLLSC)
This bit is set when the value reported in the Data Link Layer
Link Active field of the Link Status register is changed. In
response to a Data Link Layer State Changed event, software
must read the Data Link Layer Link Active field of the Link Status
register to determine if the link is active before initiating
configuration cycles to the hot plugged device.
0b Core Reserved for Electromechanical Interlock Status (EIS)
If an Electromechanical Interlock is implemented, this bit
indicates the current status of the Electromechanical Interlock.
Defined encodings are:
0b Electromechanical Interlock Disengaged
1b Electromechanical Interlock Engaged
0b Core Presence Detect State (PDS)
In band presence detect state:
0b: Slot Empty
1b: Card present in slot
This bit indicates the presence of an adapter in the slot, reflected
by the logical "OR" of the Physical Layer in-band presence detect
mechanism and, if present, any out-of-band presence detect
mechanism defined for the slot's corresponding form factor. Note
that the in-band presence detect mechanism requires that power
be applied to an adapter for its presence to be detected.
Consequently, form factors that require a power controller for
hot-plug must implement a physical pin presence detect
mechanism.
Defined encodings are:
0b Slot Empty
1b Card Present in slot
This register must be implemented on all Downstream Ports that
implement slots. For Downstream Ports not connected to slots
(where the Slot Implemented bit of the PCI Express Capabilities
Register is 0b), this bit must return 1b.
0/6/0/PCI
BA-BBh
0000h
RO; RWC
16 bits
Description
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Celeron Processor P4505, U3405 Series
Datasheet Addendum
127