Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet page 22

Table 7. Memory Channel A (Sheet 2 of 2)
Signal Name
SA_DM[7:0]
SA_DQS[8]
SA_DQS[7:0]
SA_DQS#[8]
SA_DQS#[7:0]
SA_DQ[71:64]
SA_DQ[63:0]
SA_MA[15:0]
SA_CK[1:0]
SA_CK#[1:0]
SA_CKE[1:0]
SA_CS#[1:0]
SA_ODT[1:0]
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Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
Datasheet Addendum
22
RAS Control Signal: Used with SA_CAS# and
SA_RAS# SA_WE# (along with SA_CS#) to define the SRAM
Commands.
CAS Control Signal: Used with SA_RAS# and
SA_CAS# SA_WE# (along with SA_CS#) to define the SRAM
Commands.
Data Mask: These signals are used to mask
individual bytes of data in the case of a partial
write and to interrupt burst writes. When activated
during writes, the corresponding data groups in
the SDRAM are masked. There is one SA_DM[7:0]
for every data byte lane.
ECC Data Strobe: SA_DQS[8] is the data strobe
for the ECC check data bits SA_DQ[71:64]
Note: Not required for non-ECC mode
Data Strobes: SA_DQS[7:0] and its complement
signal group make up a differential strobe pair. The
data is captured at the crossing point of
SA_DQS[7:0] and its SA_DQS#[7:0] during read
and write transactions
ECC Data Strobe Complement: SA_DQS#[8] is
the complement strobe for the ECC check data bits
SA_DQ[71:64]
Note: Not required for non-ECC mode
Data Strobe Complements: These are the
complementary strobe signals.
ECC Check Data Bits: SA_DQ[71:64] are the ECC
check data bits for Channel A.
Note: Not required for non-ECC mode
Data Bus: Channel A data signal interface to the
SDRAM data bus.
Memory Address: These signals are used to
provide the multiplexed row and column address
to the SDRAM.
SDRAM Differential Clock: Channel A SDRAM
Differential clock signal pair. The crossing of the
positive edge of SA_CK and the negative edge of
its complement SA_CK# are used to sample the
command and control signals on the SDRAM.
SDRAM Inverted Differential Clock: Channel A
SDRAM Differential clock signal-pair complement.
Clock Enable: (1 per rank) Used to:
- Initialize the SDRAMs during power-up
- Power-down SDRAM ranks
- Place all SDRAM ranks into and out of self-refresh
during STR
Chip Select: (1 per rank) Used to select particular
SDRAM components during the active state. There
is one Chip Select for each SDRAM rank.
On Die Termination: Active Termination Control.
Description
® ®
Celeron Processor P4505, U3405 Series
Document Number: 323178-003
Signal Description
Direction/Buffer
Type
O
DDR3
O
DDR3
O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
August 2010