Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet page 71

Processor Configuration Registers
Table 14. Register Terminology (Sheet 2 of 2)
Item
RW1C-S
RW-K
RW-L
RW-L-K
RW-V
RW-V-L
RW-V-L-S
RW-S
RW-O
RW-O-S
W
W1C
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Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
August 2010
Document Number: 323178-003
Read/Write 1 to Clear/Sticky bit(s). These bits can be read. Internal
events may set this bit. A software write of 1 clears (sets to 0) the
corresponding bit(s) and a write of 0 has no effect. Bits are not cleared by
"warm" reset, but is reset with a cold/complete reset (for PCI Express related
bits a cold reset is "Power Good Reset" as defined in the PCI Express Base
spec).
Read/Write/Key bit(s). These bits can be read and written by software.
Additionally this bit, when set, prohibits some other target bit field from being
writable (bit fields become Read Only).
Read/Write/Lockable bit(s). These bits can be read and written by
software. Additionally there is a Key bit (which is marked RW-K or RW-L-K)
that, when set, prohibits this bit field from being writable (bit field becomes
Read Only).
Read/Write/Lockable/Key bit(s). These bits can be read and written by
software. This bit, when set, prohibits some other bit field(s) from being
writable (bit fields become Read Only). Additionally there is a Key bit (which is
marked RW-K or RW-L-K) that, when set, prohibits this bit field from being
writable (bit field becomes Read Only).
Conceptually, this may be a cascaded lock, or it may be self-locking when in
its non-default state. When self-locking, it differs from RW-O in that writing
back the default value will not set the lock.
Write/Volatile bit(s). These bits can be read and written by software.
Hardware may set or clear the bit based on internal events, possibly sooner
than any subsequent software read could retrieve the value written.
Read/Write/Volatile/Lockable bit(s). These bits can be read and written
by software. Hardware may set or clear the bit based upon internal events,
possibly sooner than any subsequent software read could retrieve the value
written Additionally there is a bit (which is marked RW-K or RW-L-K) that,
when set, prohibits this bit field from being writable (bit field becomes Read
Only).
Read/Write/Volatile/Lockable/Sticky bit(s). These bits can be read and
written by software. Hardware may set or clear the bit based upon internal
events, possibly sooner than any subsequent software read could retrieve the
value written Additionally there is a bit (which is marked RW-K or RW-L-K)
that, when set, prohibits this bit field from being writable (bit field becomes
Read Only). These bits return to their default values on cold reset.
Read/Write/Sticky bit(s). These bits can be read and written by software.
Bits are not returned to their default values by "warm" reset, but will return to
default values with a cold/complete reset (for PCI Express related bits a cold
reset is "Power Good Reset" as defined in the PCI Express spec).
Read/Write Once bit(s). Reads prior to the first write return the default
value. The first write after warm reset stores any value written. Any
subsequent write to this bit field is ignored. All subsequent reads return the
first value written. The value returns to default on warm reset. If there are
multiple RW-O or RW-O-S fields within a DWORD, they should be written all at
once (atomically) to avoid capturing an incorrect value.
Read/Write Once/Sticky bit(s). Reads prior to the first write return the
default value. The first write after cold reset stores any value written. Any
subsequent write to this bit field is ignored. All subsequent reads return the
first value written. The value returns to default on cold reset. If there are
multiple RW-O or RW-O-S fields within a DWORD, they should be written all at
once (atomically) to avoid capturing an incorrect value.
Write-only. These bits may be written by software, but will always return
zeros when read. They are used for write side-effects. Any data written to
these registers cannot be retrieved.
Write 1 to Clear-only. These bits may be cleared by software by writing a 1.
Writing a 0 has no effect. The state of the bits cannot be read directly. The
states of such bits are tracked outside the CPU and all read transactions to the
address of such bits are routed to the other agent. Write transactions to these
bits go to both agents.
Description
® ®
Celeron Processor P4505, U3405 Series
Datasheet Addendum
71