Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet page 107

Processor Configuration Registers
Table 49. PM_CS6 - Power Management Control/Status Register
Bit Access Default
Value
1:0 RW
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Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
August 2010
Document Number: 323178-003
RST/
PWR
00b Core Power State (PS)
Indicates the current power state of this device and can be used
to set the device into a new power state. If software attempts to
write an unsupported state to this field, write operation must
complete normally on the bus, but the data is discarded and no
state change occurs.
00:
01:
10:
11:
Support of D3cold does not require any special action. While in
the D3hot state, this device can only act as the target of PCI
configuration transactions (for power management control).
This device also cannot generate interrupts or respond to MMR
cycles in the D3 state. The device must return to the D0 state in
order to be fully-functional.
When the Power State is other than D0, the bridge will Master
Abort (i.e., not claim) any downstream cycles (with exception of
type 0 config cycles).
Consequently, these unclaimed cycles will go down DMI and come
back up as Unsupported Requests, which the PROCESSOR logs as
Master Aborts in Device 0 PCISTS[13]
There is no additional hardware functionality required to support
these Power States.
Description
D0
D1 (Not supported in this device.)
D2 (Not supported in this device.)
D3
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Celeron Processor P4505, U3405 Series
Datasheet Addendum
107