Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet page 126

Table 65. SLOTCTL - Slot Control Register (Sheet 3 of 3)
Bit Access Default
Value
7:6 RO
5 RO
4 RO
3 RW
2 RO
1 RO
0 RO
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Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
Datasheet Addendum
126
RST/
PWR
00b Core Reserved for Attention Indicator Control (AIC)
If an Attention Indicator is implemented, writes to this field set
the Attention Indicator to the written state. Reads of this field
must reflect the value from the latest write, even if the
corresponding hot-plug command is not complete, unless
software issues a write without waiting for the previous
command to complete in which case the read value is undefined.
If the indicator is electrically controlled by chassis, the indicator
is controlled directly by the downstream port through
implementation specific mechanisms.
00:Reserved
01:On
10:Blink
11:Off
If the Attention Indicator Present bit in the Slot Capabilities
register is 0b, this field is permitted to be read only with a value
of 00b.
0b Core Reserved for Hot-Plug Interrupt Enable (HPIE)
When set to 1b, this bit enables generation of an interrupt on
enabled hot-plug events Default value of this field is 0b. If the
Hot Plug Capable field in the Slot Capabilities register is set to
0b, this bit is permitted to be read-only with a value of 0b.
0b Core Reserved for Command Completed Interrupt Enable (CCI)
If Command Completed notification is supported (as indicated by
No Command Completed Support field of Slot Capabilities
Register), when set to 1b, this bit enables software notification
when a hot-plug command is completed by the Hot-Plug
Controller.
Default value of this field is 0b.
If Command Completed notification is not supported, this bit
must be hard wired to 0b.
0b Core Presence Detect Changed Enable (PDCE)
When set to 1b, this bit enables software notification on a
presence detect changed event.
0b Core Reserved for MRL Sensor Changed Enable (MSCE)
When set to 1b, this bit enables software notification on a MRL
sensor changed event.
Default value of this field is 0b. If the MRL Sensor Present field in
the Slot Capabilities register is set to 0b, this bit is permitted to
be read-only with a value of 0b.
0b Core Reserved for Power Fault Detected Enable (PFDE)
When set to 1b, this bit enables software notification on a power
fault event.
Default value of this field is 0b. If Power Fault detection is not
supported, this bit is permitted to be read-only with a value of 0b
0b Core Reserved for Attention Button Pressed Enable (ABPE)
When set to 1b, this bit enables software notification on an
attention button pressed event.
Processor Configuration Registers
Description
® ®
Celeron Processor P4505, U3405 Series
Document Number: 323178-003
August 2010