Smicmd - Smi Command; Smi Command Registers - Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet

6.1.4

SMICMD - SMI Command

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively.
Note that one and only one message type can be enabled.
Table 18.

SMI Command Registers

Bit
15:12
11
10:2
1
0
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Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
Datasheet Addendum
76
Access Default
Value
RO 0h
RW 0b
RO 000h
RW 0b
RW 0b
Processor Configuration Registers
0/0/0/PCI
CC-CDh
0000h
RO, RW;
16 bits
RST/
PWR
Core Reserved
Core
SMI on Processor Thermal Sensor Trip
(TSTSMI):
1: A SMI DMI special cycle is generated by
Processor when the thermal sensor trip
requires an SMI. A thermal sensor trip point
cannot generate more than one special cycle.
0: Reporting of this condition via SMI
messaging is disabled.
Core Reserved
Core
SMI on Multiple-Bit DRAM ECC Error
(DMESMI):
1: The Processor generates an SMI DMI
message when it detects a multiple-bit error
reported by the DRAM controller.
0: Reporting of this condition via SMI
messaging is disabled. For systems not
supporting ECC this bit must be disabled.
Core
SMI on Single-bit ECC Error (DSESMI):
1: The Processor generates an SMI DMI special
cycle when the DRAM controller detects a single
bit error.
0: Reporting of this condition via SMI
messaging is disabled. For systems that do not
support ECC this bit must be disabled.
® ®
Celeron Processor P4505, U3405 Series
Description
August 2010
Document Number: 323178-003