Pci Device 6; Channel 1 Ecc Error Registers - Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
Table 22.

Channel 1 ECC Error Registers

Bit
63:48
47:32
31:29
28:27
26:24
23:16
15:2
1
0
6.2

PCI Device 6

Device 6 contains the controls associated with the PCI Express x8 port (Port 1) that is
enabled with bifurcation of the PCI Express x16 root port.
Warning: When reading the PCI Express "conceptual" registers such as this, you may not get a
valid value unless the register value is stable.
The PCI Express based specification defines two types of reserved bits.
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Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
August 2010
Document Number: 323178-003
Default
Access
Value
RO-V-S 0000h
RO-V-S 0000h
RO-V-S 000b
RO-V-S 00b
RO 000b
RO-V-S 00b
RO 0000h
RO-V-S 0b
RO-V-S 0b
RST/
PWR
Core Error Column Address (ERRCOL):
Row address of the address block of main
memory of which an error (single bit or multi-
bit error) has occurred.
Core Error Row Address (ERRROW):
Row address of the address block of main
memory of which an error (single bit or multi-
bit error) has occurred
Core Error Bank Address (ERRBANK):
Rank address of the address block of main
memory of which an error (single bit or multi-
bit error) has occurred
Core Error Rank Address (ERRRANK):
Rank address of the address block of main
memory of which an error (single bit or multi-
bit error) has occurred.
Core Reserved
Core Error Syndrome (ERRSYND):
Syndrome that describes the set of bits
associated with the first failing quadword
Core Reserved
P
Core Multiple Bit Error Status (MERRSTS):
This bit is set when an uncorrectable multiple-
bit error occurs on a memory read data
transfer. When this bit is set, the address that
caused the error and the error syndrome are
also logged and they are locked until this bit is
cleared. This bit is cleared when it receives an
indication that the CPU has cleared the
corresponding bit in the ERRSTS register.
Core Correctable Error Status (CERRSTS):
This bit is set when a correctable single-bit
error occurs on a memory read data transfer.
When this bit is set, the address that caused
the error and the error syndrome are also
logged and they are locked to further single bit
errors, until this bit is cleared. But, a multiple
bit error that occurs after this bit is set will
over-write the address/error syndrome info.
This bit is cleared when it receives an indication
that the CPU has cleared the corresponding bit
in the ERRSTS register.
® ®
Celeron Processor P4505, U3405 Series
Description
Datasheet Addendum
81