Ssts6 - Secondary Status; Ssts6 - Secondary Status Register - Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
6.2.14

SSTS6 - Secondary Status

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
SSTS6 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (i.e., PCI Express-G side) of the "virtual" PCI-to-PCI
bridge embedded within processor.
Table 37.

SSTS6 - Secondary Status Register

Bit Access Default
Value
15 RWC
14 RWC
13 RWC
12 RWC
11 RO
10:9 RO
8 RWC
7 RO
6 RO
5 RO
4:0 RO
® TM
Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
August 2010
Document Number: 323178-003
RST/
PWR
0b Core Detected Parity Error (DPE)
This bit is set by the Secondary Side for a Type 1 Configuration
Space header device whenever it receives a Poisoned TLP,
regardless of the state of the Parity Error Response Enable bit in
the Bridge Control Register.
0b Core Received System Error (RSE)
This bit is set when the Secondary Side for a Type 1 configuration
space header device receives an ERR_FATAL or ERR_NONFATAL.
0b Core Received Master Abort (RMA)
This bit is set when the Secondary Side for Type 1 Configuration
Space Header Device (for requests initiated by the Type 1 Header
Device itself) receives a Completion with Unsupported Request
Completion Status.
0b Core Received Target Abort (RTA)
This bit is set when the Secondary Side for Type 1 Configuration
Space Header Device (for requests initiated by the Type 1 Header
Device itself) receives a Completion with Completer Abort
Completion Status.
0b Core Signaled Target Abort (STA)
Not Applicable or Implemented. Hard wired to 0. The processor
does not generate Target Aborts (the processor will never
complete a request using the Completer Abort Completion
status).
00b Core DEVSELB Timing (DEVT)
Not Applicable or Implemented. Hard wired to 0.
0b Core Master Data Parity Error (SMDPE)
When set indicates that the PROCESSOR received across the link
(upstream) a Read Data Completion Poisoned TLP (EP=1). This
bit can only be set when the Parity Error Enable bit in the Bridge
Control register is set.
0b Core Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hard wired to 0.
0b Core Reserved
0b Core 66-/60-MHz Capability (CAP66)
Not Applicable or Implemented. Hard wired to 0.
00h Core Reserved
0/6/0/PCI
1E-1Fh
0000h
RWC; RO
16 bits
Description
® ®
Celeron Processor P4505, U3405 Series
Datasheet Addendum
95