Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet page 79

Processor Configuration Registers
Table 20. Channel 0 ECC Error Registers (Sheet 2 of 2)
Bit
0
® TM
Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
August 2010
Document Number: 323178-003
Default
Access
Value
RO-P 0b
RST/
PWR
Core Correctable Error Status (CERRSTS):
This bit is set when a correctable single-bit
error occurs on a memory read data transfer.
When this bit is set, the address that caused
the error and the error syndrome are also
logged and they are locked to further single bit
errors, until this bit is cleared. But, a multiple
bit error that occurs after this bit is set will
over-write the address/error syndrome info.
This bit is cleared when it receives an indication
that the CPU has cleared the corresponding bit
in the ERRSTS register.
® ®
Celeron Processor P4505, U3405 Series
Description
Datasheet Addendum
79