System Bus Ac Specifications (Clock) At The Processor Edge Fingers (For S.e - Intel CELERON 1.10 GHZ Datasheet

Table 9. System Bus AC Specifications (Clock) at the Processor Edge Fingers
(for S.E.P. Package)
System Bus Frequency
T1': BCLK Period
T1B': SC242 to Core Logic BCLK Offset
T2': BCLK Period Stability
T3': BCLK High Time
T4': BCLK Low Time
T5': BCLK Rise Time
T6': BCLK Fall Time
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 0.70 V at the processor edge
fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the
processor core to receive the signal with a reference at 1.25 V. All AGTL+ signal timings (address bus, data
bus, etc.) are referenced at 1.00 V at the processor edge fingers.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.70 V at the processor edge
fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the
processor core to receive the signal with a reference at 1.25 V. All CMOS signal timings (compatibility
signals, etc.) are referenced at 1.25 V at the processor edge fingers.
4. The internal core clock frequency is derived from the Intel Celeron processor system bus clock. The system
bus clock to core clock ratio is determined during initialization.
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
6. This specification applies to Intel Celeron processors when operating at a system bus frequency of 66 MHz.
7. The BCLK offset time is the absolute difference needed between the BCLK signal arriving at the Intel Celeron
processor edge finger at 0.5 V vs. arriving at the core logic at 1.25 V. The positive offset is needed to account
for the delay between the SC242 connector and processor core. The positive offset ensures both the
processor core and the core logic receive the BCLK edge concurrently.
8. See Section 3.1
9. Not 100% tested. Specified by design characterization as a clock driver requirement.
Datasheet
T# Parameter
for Intel Celeron processor system bus clock signal quality specifications.
®
Intel Celeron
Min Nom Max Unit
66.67 MHz
15.0
0.78
± 300
4.44
4.44
0.84 2.31
0.84 2.31
Table 12
®
Processor up to 1.10 GHz
Figure Notes
ns 3 4, 5, 6
ns 3 Absolute Value
ps See Table 10
6
ns 3 @>2.0 V
6
ns 3 @<0.5 V
ns 3 (0.5 V–2.0 V)
ns 3 (2.0 V–0.5 V)
shows the supported ratios for each
7,8
6, 9
6, 9
35