Intel SL3VS - Celeron 633 MHz Processor Specification
  1. Manuals
  2. Brands
  3. Intel Manuals
  4. Computer Hardware
  5. SL3VS - Celeron 633 MHz Processor
  6. Specification
Intel SL3VS - Celeron 633 MHz Processor Specification

Intel SL3VS - Celeron 633 MHz Processor Specification

Specification update
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
®
®
Intel
Celeron
Processor
Specification Update
Release Date: August 2007
Document Number: 243748-051
®
®
The Intel
Celeron
processor may contain design defects or errors known as errata, which may cause the
product to deviate from published specifications. Current characterized errata are documented in this
Specification Update.

Advertisement

Table of Contents
loading

Related Manuals for Intel SL3VS - Celeron 633 MHz Processor

Summary of Contents for Intel SL3VS - Celeron 633 MHz Processor

  • Page 1 Release Date: August 2007 Document Number: 243748-051 ® ® The Intel Celeron processor may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
  • Page 2 Intel, Pentium, Celeron, Intel Xeon and the Intel logo are trademarks or registered trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries*Other names and brands may be claimed as the property of others.

  • Page 3: Table Of Contents

    Processor................... 1 GENERAL INFORMATION..........................1 Intel ® Celeron ® Processor and Boxed Intel ® Celeron ® Processor Markings (S.E.P. Package)....1 Intel ® Celeron ® Processor and Boxed Intel ® Celeron ® Processor Markings (PPGA Package)....2 Intel ® Celeron ® Processor and Boxed Intel ® Celeron ® Processor Markings (FC-PGA/FC-PGA2 Package) 3 IDENTIFICATION INFORMATION ........................

  • Page 4: Revision History

    INTEL CELERON PROCESSOR SPECIFICATION UPDATE REVISION HISTORY Date of Revision Version Description April 1998 -001 This document is the first Specification Update for the Intel ® Celeron processor. May 1998 -002 Added Errata 24 through 28. June 1998 -003 Updated S-spec Table. Updated Summary Table of Changes.
  • Page 5 Processor Identification Information table Added Errata C75 and C76. December 2000 -031 Updated Specification Update product key to include the Intel® Pentium® 4 processor, Updated Erratum C2. Added Documentation changes C11, C12, C13, C14, C15 and C16. Updated the Intel ® Celeron...
  • Page 6 Updated the Summary of Errata table. August 2001 -036 Added Errata C79 and C80. Updated the Summary of changes section. August 2001 -037 Out of cycle release. Updated the Intel ® ® Celeron Processor Identification Information table October 2001 -038 Updated the identification information section with 0.13 micron...
  • Page 7 ® ® INTEL CELERON PROCESSOR SPECIFICATION UPDATE REVISION HISTORY Date of Revision Version Description August 2007 -051 Updated Summary Table of Changes. Added Erratum C111.

  • Page 8: Preface

    Intel • Intel® 64 and Intel IA-32 Architectures Software Developer’s Manual, Volumes 1, 2-A, 2-B, 3-A and 3-B (Document numbers 253665, 253666, 253667, 253668, and 253669, respectively.) It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

  • Page 9: Specification Update For The Intel ® Celeron ® Processor

    ® ® Specification Update for the Intel Celeron Processor GENERAL INFORMATION Inte Celeron Processor and Boxed Inte Celeron Processor ® ® ® ® Markings (S.E.P. Package) Static White Silkscreen marks celeron ™ ® Dynamic laser mark area NOTES: • SYYYY = S-spec Number.

  • Page 10: Intel Celeron Processor And Boxed Intel Celeron Processor Markings (Ppga Package)

    ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Intel Celeron Processor and Boxed Intel Celeron Processor ® ® ® ® Markings (PPGA Package) Bottom int l ® celeron AAAAAAAZZZ LLL SYYYY Country of Origin FFFFFFFF-XXXX ’98 NOTES: AAAAAAA = Product Code ZZZ = Processor Speed (MHz)

  • Page 11: Intel ® Celeron ® Processor And Boxed Intel ® Celeron ® Processor Markings (Fc-Pga/Fc-Pga2 Package)

    FC-PGA 370 Pin Package GRP1LN1: INTEL (m)(c) '01_-_{COO} GRP1LN2: {Core Freq}/{Cache}/{Bus Freq}/{Voltage} GRP2LN1: {FPO}-{S/N} GRP2LN2: CELERON {S-Spec} FC-PGA2 370 Pin Package GRP1LN1 GRP1LN2 GRP1LN1: INTEL (m)(c) '01_-_{Country of Origin} GRP1LN2: {Core freq}/{Cache}/{Bus Freq}/{Voltage} GRP2LN1: {FPO}-{S/N} GRP2LN2: CELERON {S-Spec} GRP2LN1 GRP2LN2...

  • Page 12: Identification Information

    8 through 15 and bits 0 through 7. Software must compare the value contained in each of the descriptor bit fields according to the definition of the CPUID instruction . For more details refer to the AP-485 Intel Processor Identification...
  • Page 13 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE ® ® Intel Celeron Processor Identification Information L2 Cache Package Core Size Speed (MHz) S-Spec Stepping (Kbytes) CPUID Core/Bus Revision Notes SL2SY 0650h 266/66 SEPP Rev. 1 SL2YN 0650h 266/66 SEPP Rev. 1 SL2YP...
  • Page 14 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE ® ® Intel Celeron Processor Identification Information L2 Cache Package Core Size Speed (MHz) S-Spec Stepping (Kbytes) CPUID Core/Bus Revision Notes SL3A2 0665h 400/66 PPGA SL37X 0665h 400/66 PPGA SL3BA 0665h 433/66 PPGA SL3BS...
  • Page 15 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE ® ® Intel Celeron Processor Identification Information L2 Cache Package Core Size Speed (MHz) S-Spec Stepping (Kbytes) CPUID Core/Bus Revision Notes SL48F 0683h 700/66 FC-PGA SL4EG 0683h 700/66 FC-PGA SL4P8 0686h 700/66 FC-PGA 2, 4, 5...
  • Page 16 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE ® ® Intel Celeron Processor Identification Information L2 Cache Package Core Size Speed (MHz) S-Spec Stepping (Kbytes) CPUID Core/Bus Revision Notes SL634 068Ah 950/100 FC-PGA2 2,8,14...
  • Page 17 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE ® ® Intel Celeron Processor Identification Information L2 Cache Package Core Size Speed (MHz) S-Spec Stepping (Kbytes) CPUID Core/Bus Revision Notes SL5XT 068Ah 1 GHz/100 FC-PGA 8,11 SL5XQ 068Ah 1 GHz/100 FC-PGA 2, 8,11...
  • Page 18 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE ® ® Intel Celeron Processor Identification Information L2 Cache Package Core Size Speed (MHz) S-Spec Stepping (Kbytes) CPUID Core/Bus Revision Notes SL6C6 06B4h 1.40 FC-PGA2 14, 15 GHz/100 SL6JU 06B4h 1.40 FC-PGA2 2,14, 15...

  • Page 19: Summary Of Changes

    The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Celeron processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted. This table uses the following...

  • Page 20: Summary Of Errata

    AF = Dual-Core Intel Xeon processor LV ® ® AG = Dual-Core Intel Xeon Processor 5100 Series AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology ® Δ ® Δ AI = Intel Core™2 Extreme Processor X6800 and Intel Core™2 Duo Desktop Processor E6000...
  • Page 21 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata CPUID/Stepping Plans ERRATA 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h cache line replacement Fixed Potential early deassertion of LOCK# during split-lock cycles Fixed A20M# may be inverted after returning from and Reset...
  • Page 22 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata CPUID/Stepping Plans ERRATA 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h Fixed Test pin must be high during power up Fixed Intervening writeback may occur during locked transaction NoFix MC2_STATUS MSR has...
  • Page 23 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata CPUID/Stepping Plans ERRATA 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h Fixed Incorrect chunk ordering may prevent execution of the machine check exception handler after BINIT# Fixed UC write may be reordered...
  • Page 24 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata CPUID/Stepping Plans ERRATA 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h NoFix FLUSH# servicing delayed while waiting for STARTUP_IPI in 2-way MP systems NoFix Double ECC error on read may result in BINIT#...
  • Page 25 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata CPUID/Stepping Plans ERRATA 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h NoFix Snoop probe during FLUSH# could cause L2 to be left in shared state Fixed Livelock May Occur Due to...
  • Page 26 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata CPUID/Stepping Plans ERRATA 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h SLP# is Asserted Low NoFix Incorrect assertion of THERMTRIP# Signal NoFix Under some complex conditions, the Instructions in the shadow of a JMP FAR...
  • Page 27 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata CPUID/Stepping Plans ERRATA 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h (Uncacheable) May Consolidate to UC Under Certain Conditions LTR NoFix (Load Task Register) Instruction May Result in System Hang...
  • Page 28 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata CPUID/Stepping Plans ERRATA 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h Have Not Occurred Using 2M/4M Pages When A20M# Is Asserted May C101 NoFix Result in Incorrect Address Translations Values for LBR/BTS/BTM will...

  • Page 29: Summary Of Documentation Changes

    ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE * Fix will be only on Celeron processors with CPUID=068xh. Summary of Documentation Changes CPUID/Stepping DOCUMENTATION 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h Plans CHANGES SSE and SSE2 Instructions Opcodes Executing the SSE2 Variant...
  • Page 30 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Documentation Changes CPUID/Stepping DOCUMENTATION 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h Plans CHANGES Cache Description Instruction Formats and Encoding Machine-Check Initialization...

  • Page 31: Summary Of Specification Clarifications

    ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Specification Clarifications CPUID/Stepping SPECIFICATION 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h Plans CLARIFICATIONS PWRGOOD inactive pulse width Floating-point opcode clarification MTRR initialization clarification Non-AGTL+ output low current clarification...

  • Page 32: Summary Of Specification Changes

    ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Specification Changes CPUID/Stepping SPECIFICATION 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h Plans CHANGES RESET# pin definition Tco max revision for 533A,566 & 600MHz Processor thermal specification change and TDP redefined...

  • Page 33: Errata

    Wrapping an 80-bit floating-point load around a segment boundary in this way is not a normal programming practice. Intel has not currently identified any software which exhibits this behavior. If the FP Data Operand Pointer is used in an OS which may run 16-bit floating-point code, Workaround: care must be taken to ensure that no 80-bit floating-point accesses are wrapped around a 64-Kbyte boundary.

  • Page 34: Debug Exception

    Case 5: When an instruction that accesses a debug register is executed, and a breakpoint is encountered on the instruction, the breakpoint is reported twice. Case 6: Unlike previous versions of Intel Architecture processors, Celeron processors will not set the Bi bits for a matching disabled breakpoint unless at least one other breakpoint is enabled.
  • Page 35 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE FP Inexact-Result Exception Flag May Not Be Set When the result of a floating-point operation is not exactly representable in the destination format Problem: (1/3 in binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is normally set by the processor.
  • Page 36 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE I/O Restart in SMM May Fail After Simultaneous MCE If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the Problem: data for this instruction becomes corrupted, the Celeron processor will signal a machine check exception (MCE).
  • Page 37 Although BTMs may not be entirely reliable due to this erratum, the conditions necessary for Implication: this boundary condition to occur have only been exhibited during focused simulation testing. Intel has currently not observed this erratum in a system level validation environment.
  • Page 38 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C11. Potential Early Deassertion of LOCK# During Split-Lock Cycles During a split-lock cycle there are four bus transactions: 1st ADS# (a partial read), 2nd ADS# (a Problem: partial read), 3rd ADS# (a partial write), and the 4th ADS# (a partial write). Due to this erratum, LOCK# may deassert one clock after the 4th ADS# of the split-lock cycle instead of after the 4th RS# assertion corresponding to the 4th ADS# has been sampled.
  • Page 39 Intel has observed this erratum only in a focused testing environment. Intel has not observed any commercially available operating system, application, or compiler that makes use of or generates this instruction.
  • Page 40 Cache State Corruption in the Presence of Page A/D-bit Setting and Snoop Traffic If an operating system uses the Page Access and/or Dirty bit feature implemented in the Intel Problem: architecture and there is a significant amount of snoop traffic on the bus, while the processor is setting the Access and/or Dirty bit the processor may inappropriately change a single L1 cache line to the modified state.
  • Page 41 Floating-point routines commonly leave TOS to 0 prior to exiting. For a store to be executed as the first MMX instruction in an MMX technology routine following a floating-point routine, the software would be implementing instruction level intermixing of floating-point and MMX instructions. Intel does not recommend this practice.
  • Page 42 An OS can prevent old data from being stored to a new task’s program state by cleansing the FPU explicitly after every task switch. Follow Intel’s recommended programming paradigms in the Intel Architecture Developer’s Optimization Manual for writing MMX technology programs. Specifically, do not mix floating-point and MMX instructions.
  • Page 43 Reset without first executing an FINIT/FNINIT instruction will use an incorrect value, resulting in incorrect behavior of the software. Software should follow the recommendation in Section 8.2 of the Intel Architecture Software Workaround: Developer’s Manual, Volume 3: System Programming Guide (Order Number 243192). This recommendation states that if the FPU will be used, software-initialization code should execute an FINIT/FNINIT instruction following a hardware reset.
  • Page 44 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C23. MOVD Following Zeroing Instruction Can Cause Incorrect Result An incorrect result may be calculated after the following circumstances occur: Problem: 1. A register has been zeroed with either a SUB reg, reg instruction or an XOR reg, reg instruction, 2.
  • Page 45 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE There are two possible workarounds for this erratum: Workaround: 1. Rather than using the MOVSX-MOVD or CBW-MOVD pairing to handle one variable at a time, use the sign extension capabilities (PSRAW, etc.) within MMX technology for operating on multiple variables. This would result in higher performance as well.
  • Page 46 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C25. Read Portion of RMW Instruction May Execute Twice When the Celeron processor executes a read-modify-write (RMW) arithmetic instruction, with Problem: memory as the destination, it is possible for a page fault to occur during the execution of the store on the memory operand after the read operation has completed but before the write operation completes.
  • Page 47 When in V86 mode, if a MOV instruction is executed on debug registers, a general-protection Problem: exception (#GP) should be generated, as documented in the Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide , Section 15.2. However, in the case when the general detect enable flag (GD) bit is set, the observed behavior is that a debug exception (#DB) is generated instead.
  • Page 48 Page Attribute Table (PAT) entries are left in their default setting, which includes UC- memory type (PCD = 1, PWT = 0; see the Intel Architecture Software Developer’s Manual, Volume 3: System Programming Guide, for details), data for entries set to UC- will be cached as if the memory type were writeback (WB).
  • Page 49 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C32. Misprediction in Program Flow May Cause Unexpected Instruction Execution To optimize performance through dynamic execution technology, the P6 architecture has the Problem: ability to predict program flow. In the event of a misprediction, the processor will normally clear the incorrect prediction, adjust the EIP to the correct location, and flush out any instructions it may have fetched from the misprediction.
  • Page 50 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE All bus agents that support system bus ECC must disable it when a 2:1 ratio is used. Workaround: For the steppings affected see the Summary of Changes at the beginning of this section. Status: C35.
  • Page 51 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C37. SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment Selector” to SS and CS Registers According to the processor specification, attempting to load a null segment selector into the CS Problem: and SS segment registers should generate a General Protection Fault (#GP). Although loading a null segment selector to the other segment registers is allowed, the processor will generate an exception when the segment register holding a null selector is used to access memory.
  • Page 52 If an OS is used which can clear the D-bit for system pages, and which jumps to a new TSS on Implication: a task switch, then a condition may occur which results in a system hang. Intel has not identified any commercial software which may encounter this condition; this erratum was discovered in a focused testing environment.
  • Page 53 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C41. UC Write May Be Reordered Around a Cacheable Write After a write occurs to a UC (uncacheable) region of memory, there exists a small window of Problem: opportunity where a subsequent write transaction targeted for a UC memory region may be reordered in front of a write targeted to a region of cacheable memory.
  • Page 54 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C43. Internal Cache Protocol Violation May Cause System Hang A Celeron processor-based system may hang due to an internal cache protocol violation. During Problem: multiple transactions targeted at the same cacheline, there exists a small window of time such that the processor's internal timings align to create a livelock situation.
  • Page 55 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C45. Machine Check Exception May Occur Due to Improper Line Eviction in the IFU The Celeron processor is designed to signal an unrecoverable Machine Check Exception (MCE) Problem: as a consistency checking mechanism. Under a complex set of circumstances involving multiple speculative...
  • Page 56 Programmers should use the cross modifying code synchronization algorithm as detailed in Workaround: Volume 3 of the Intel Architecture Software Developer's Manual , section 7.1.3, in order to avoid this erratum. For the steppings affected see the Summary of Changes at the beginning of this section.
  • Page 57 These combinations are not normally generated in the course of software programming, nor are such sequences known by Intel to be generated in commercially available software and tools. Development tools (compilers, assemblers) do not generate this type of code sequence, and will normally flag such a sequence as an error.
  • Page 58 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C51. Floating-Point Exception Condition May be Deferred A floating-point instruction that causes a pending floating-point exception (ES=1) is normally Problem: signaled by the processor on the next waiting FP/MMX™ technology instruction. In the following set of...
  • Page 59 FLUSH# assertion at this point. The FLUSH# will be serviced as soon as the processor is awakened by a STARTUP_IPI, before any other instructions are executed. Intel has not encountered any operating systems that are affected by this erratum.
  • Page 60 “lazy” TLB shootdowns. The memory image of the EFLAGS register on the page fault handler’s stack prematurely contains the final arithmetic flag values although the instruction has not yet completed. Intel has not identified any operating systems that inspect the arithmetic portion of the EFLAGS register during a page fault nor observed this erratum in laboratory testing of software applications.
  • Page 61 (if the conditions above are satisfied). Intel has only encountered this problem in focus testing with artificially generated external events. Intel has not currently identified any commercial software which exhibits this problem.
  • Page 62 This erratum does not affect uniprocessor systems. The existence of this erratum was discovered during ongoing design reviews but it has not as yet been reproduced in a lab environment. Intel has not identified, to date, any commercially available application or operating system software which is affected by this erratum. If the erratum does occur one processor may execute software with the stale data that was present from the previous shared state rather than the data written more recently by another processor.
  • Page 63 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C61. Memory Ordering Based Synchronization May Cause a Livelock Condition in MP Systems In an MP environment, the following sequence of code (or similar code) in two processors (P0 and Problem: P1) may cause them to each enter an infinite loop (livelock condition):...
  • Page 64 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C62. Processor May Assert DRDY# on a Write With No Data When a MASKMOVQ instruction is misaligned across a chunk boundary in a way that one chunk Problem: has a mask of all 0’s, the processor will initiate two partial write transactions with one having all byte enables deasserted.
  • Page 65 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE For the steppings affected, see the Summary of Changes at the beginning of this section. Status: C66. MASKMOVQ Instruction Interaction with String Operation May Cause Deadlock Under the following scenario, combined with a specific alignment of internal events, the processor...
  • Page 66 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE or IMUL AX, word ptr <memory address> (opcode 0F AF /r) or IMUL AX, BX, 16 (opcode 6B /r ib) or IMUL AX, word ptr <memory address>, 16 (opcode 6B /r ib) or IMUL AX, 8 (opcode 6B /r ib) or IMUL AX, BX, 1024 (opcode 69 /r iw) or IMUL AX, word ptr <memory address>, 1024 (opcode 69 /r iw)
  • Page 67 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE *Note: MOV EAX, EAX is used here in a generic sense. Again, EAX can be substituted with any 32-bit register. Status: For the steppings affected see the Summary of Changes at the beginning of this section.
  • Page 68 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C70. Selector for the LTR/LLDT Register May Get Corrupted The internal selector portion of the respective register (TR, LDTR) may get corrupted if, during a Problem: small window of LTR or LLDT system instruction execution, the following sequence of events occur: Speculative write to a segment register that might follow the LTR or LLDT instruction The read segment descriptor of LTR/LLDT operation spans a page (4 Kbytes) boundary;...
  • Page 69 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C73. Memory Aliasing with Inconsistent A and D bits May Cause Processor Deadlock In the event that software implements memory aliasing by having two Page Directory Problem: Entries(PDEs) point to a common Page Table Entry(PTE) and the Accessed and Dirty bits for the two PDEs are allowed to become inconsistent, the processor may become deadlocked.
  • Page 70 Interleaved instruction fetches between different memory types may result in a machine check Implication: exception. The system may hang if machine check exceptions are disabled. Intel has not observed the occurrence of this erratum while running commercially available applications or operating systems.
  • Page 71 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C79. The instruction Fetch Unit (IFU) May Fetch Instructions Based Upon Stale CR3 Data After a Write to CR3 Register Problem: Under a complex set of conditions, there exists a one clock window following a write to the CR3 register where-in it is possible for the iTLB fill buffer to obtain a stale page translation based on the stale CR3 data.
  • Page 72 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C82. Incorrect Assertion of THERMTRIP# Signal Problem: The internal control register bit responsible for operation of the Thermtrip circuit functionality may power up in a non-initialized state. As a result, THERMTRIP# may be incorrectly asserted during de-assertion of RESET# at nominal operating temperatures.
  • Page 73 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Figure 1 Celeron® on 0.13 Micron Processor 256K Platforms Workaround 2.5V 330 ohm PW RGD For Production Boards: Depopulate R5 PGA370 510 ohm To use ITP: Install R5, Depopulate R4 0 ohm 1.3K ohm 39 ohm •...
  • Page 74 JMP FAR instruction could be unintentionally executed. Implication: Occurrence of this erratum could lead to erroneous software behavior. Intel has not identified any commercial software which may encounter this condition; this erratum was discovered in a focused test environment.
  • Page 75 An instruction with lock data access that spans across two pages may, given some rare internal conditions, hang the system. Implication: When this erratum occurs, the system may hang. Intel has not observed this erratum with any commercially available software or system.
  • Page 76 Implication: The impact of this store ordering behavior may vary from normal software execution to potential software failure. Intel has not observed this erratum in commercially available software. Workaround: FXSAVE, STOS, or MOVS data must not cross page boundary from WB to UC memory type.
  • Page 77 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system. Workaround: Avoid code that wraps around segment limit.
  • Page 78 For a page whose PAT memory type is USWC while the relevant MTRR memory type is UC, the consolidated memory type may be treated as UC (rather than WC as specified in IA-32 Intel® Architecture Software Developer's Manual).. Implication: When this erratum occurs, the memory page may be treated as UC (rather than WC).
  • Page 79 Executing any non-control FP instruction with memory operand will initialize the FPUDataPointer. Intel has not observed this erratum with any commercially available software. Workaround: After initialization, do not expect the FPUDataPointer in a floating point state or...
  • Page 80 Invalid entries in the Page-Directory-Pointer-Table Register (PDPTR) that have the reserved bits set to one may cause a General Protection (#GP) exception. Implication: Intel has not observed this erratum with any commercially available software. Workaround: Do not set the reserved bits to one when PDPTR entries are invalid.
  • Page 81 #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 82 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE • a linear address has bit 20 set • the address references a large page • A20M# is enabled Implication: When A20M# is enabled and an address references a large page the resulting translated physical address may be incorrect. This erratum has not been observed with any commercially available operating system.
  • Page 83 Problem: Under certain conditions as described in the Software Developers Manual section “Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions...
  • Page 84 Implication: instruction. Please refer to "Procedure Calls For Block-Structured Languages" in IA-32 Intel® Architecture Software Developer’s Manual, Vol. 1, Basic Architecture, for information on the usage of the ENTER instructions. This erratum is not expected to occur in ring 3.
  • Page 85 Stale translations may remain valid in TLB after a PTE update resulting in unpredictable Implication: system behavior. Intel has not observed this erratum with any commercially available software. Software should ensure that the memory type specified in the MTRRs is the same for the Workaround: entire address range of the large page.
  • Page 86 The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX Implication: may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software. None identified.

  • Page 87: Documentation Changes

    All Documentation Changes will be incorporated into a future version of the appropriate Celeron processor documentation. SSE and SSE2 Instructions Opcodes The note at the end of section 2.2 in the Intel Architecture Software Developer's Manual , Vol 2 : Instruction Set Reference states: NOTE: Some of the SSE and SSE2 instructions have three-byte opcodes.
  • Page 88 Executing the SSE2 Variant on a Non-SSE2 Capable Processor In Intel Architecture Software Developer's Manual, Vol 2 : Instruction Set Reference the section for each of the following instructions states that executing the instruction in real or protected mode on a processor for which the SSE2 feature flag returned by CPUID is 0 (SSE2 not supported by the processor) will result in the generation of an undefined opcode exception (#UD).
  • Page 89 ; otherwise, set to 0. Incorrect Description of stack The IA-32 Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture Chapter 6, Section 6.2 paragraph 2, labeled “STACK” currently states: The next available memory location on the stack is called the top of stack. At any given time, the stack pointer (contained in the ESP register) gives the address (that is the offset from the base of the SS segment) of the top of the stack.
  • Page 90 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE EFLAGS Register Correction The Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture Section 3.7.2, Figure 3.7. “EFLAGS Register” currently states: Bit 11 “OF” as “X” It should state: Bit 11 “OF” as “S”...
  • Page 91 C11. LGDT/LIDT Instruction Information Correction In the Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference, the sentence in the LGDT/LIDT instruction section currently states: ”See 'SFENCE -- Store Fence' in this chapter for information on storing the contents of the GDTR and IDTR."...
  • Page 92 INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C12. Errors in Instruction Set Reference The following changes will be made to the Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference: Page 3-586 “PMULUDQ—Multiply Packed Unsigned Doubleword Integers” currently states: 66 OF F4 /r...
  • Page 93 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE PMOVMSKB (66) Gd, Vdq 5 . Page A-10, Table A-3, Two-byte Opcode Map:80H-7FH (First Byte is 0FH). Entry F7 currently states: MASKMOVQ Ppi, Qpi MASKMOVQU (66) Vdq, Wdq It should state: MASKMOVQ Ppi, Qpi...
  • Page 94 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE PMULH – Packed multiplication It should state: PMULHW – Packed multiplication, store high word 10. Page B-21, Table B-12, MMX Instruction Formats and Encodings (Contd.). Add instruction PMULHUW : PMULHUW – Packed multiplication, store high word (unsigned)
  • Page 95 It should state: PMULLW – Packed multiplication, store low word C13. RSM Instruction Set Summary The Intel Architecture Software Developer's Manual, Vol 1: Basic Architecture Section 5.8 "INSTRUCTION SET SUMMARY” currently states: Return from system management mode (SSM) It should state: Return from system management mode (SMM) C14.
  • Page 96 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C15. DAA—Decimal Adjust AL after Addition The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference page 3-173 currently states: Operation IF (((AL AND 0FH) > 9) or AF = 1) THEN AL ← A L + 6;...
  • Page 97 INTEL CELERON® PROCESSOR SPECIFICATION UPDATE C16. DAS—Decimal Adjust AL after Subtraction The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference , on page 3-175 currently states: Operation IF (AL AND 0FH) > 9 OR AF = 1 THEN AL ←...
  • Page 98 CELERON® PROCESSOR SPECIFICATION UPDATE C17. Omission of Dependency Between BTM and LBR The Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide Chapter 15 , Section 5.3, on page 15-15 currently states: 15.5.3. Monitoring Branches, Exceptions, and Interrupts (Pentium...
  • Page 99 I/O Permissions Bitmap Base Addy > 0xDFFF Does not Cause #GP(0) Fault The Intel Architecture Software Developer's Manual, Vol 1: Basic Architecture, page 12-6, section 12.5.2, last paragraph currently states: If the I/O bit map base address is greater than or equal to the TSS segment limit, there is no I/O permission map, and all I/O instructions generate exceptions when the CPL is greater than the current IOPL.
  • Page 100 C21. I/O Permission Bit Map The Intel Architecture Software Developer's Manual, Vol 1: Basic Architecture Chapter 12, section 12.5.2 on Figure 12-2 (I/O Permission Bit Map) currently states: Last byte of bit map must be followed by a byte with all bits.
  • Page 101 The pseudocode assumes that the machine-check exception (#MC) handler has been installed on the system. This initialization procedure is compatible with the Pentium 4, Intel Xeon, P6 family, and Pentium processors.
  • Page 102 Example gives pseudocode for performing this initialization. This pseudocode checks for the existence of the machine-check architecture and exception on the processor, then enables the machine-check exception and the error-reporting register banks. The pseudocode shown is compatible with the Pentium 4, Intel Xeon, P6 family, and Pentium processors.
  • Page 103 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE Example . In addition, when using P6 family processors, the software must set MCi_STATUS registers to 0 when doing a soft-reset. Machine-Check Initialization Pseudocode Check CPUID Feature Flags for MCE and MCA support IF CPU supports MCE...
  • Page 104 ® INTEL CELERON® PROCESSOR SPECIFICATION UPDATE FOR error-reporting banks (0 through MAX_BANK_NUMBER) IA32_MCi_STATUS <-- 0; ELSE FOR error-reporting banks (0 through MAX_BANK_NUMBER) (Optional for BIOS and OS) Log valid errors (OS only) IA32_MCi_STATUS <-- 0; Setup the Machine Check Exception (#MC) handler for vector 18 in IDT...

  • Page 105: Specification Clarifications

    Celeron Processor Datasheet • Intel® 64 and IA-32 Architectures Software Developer’s Manual , Volumes 1, 2A, 2B, 3A and 3B. All Specification Clarifications will be incorporated into a future version of the appropriate Celeron processor documentation. PWRGOOD Inactive Pulse Width...
  • Page 106 FSTSW AX MTRR Initialization Clarification The following sentence should be added to the end of the first paragraph of Section 9.12.5 of the Intel Architecture Software Developer’s Manual , Volume 3: System Programming Guide: “The MTRRs must be disabled prior to initialization or modification.”...

  • Page 107: Specification Changes

    ® Celeron will be updated to reflect this change. Intel has verified that flexible motherboard designs which follow Intel’s recommended layout guidelines will not be impacted by these new specifications. For customers who have designs aimed to support ONLY the Coppermine-128K processors 533A, 566 &...
  • Page 108 The TDP values represent the thermal design point required to cool Celeron processors in the platform environment. This replaces column 3 and column 4, Processor Power and Processor Core Power, from Table 37 of the Intel ® ®...

This manual is also suitable for:

Celeron

Table of Contents