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Table 29. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins
(for the FC-PGA/FC-PGA2 Packages)
V1: BCLK V
V1: PICCLK V
V2: BCLK V
V2: PICCLK V
V3: V
Absolute Voltage Range
IN
V4: BCLK Rising Edge Ringback
V4: PICCLK Rising Edge Ringback
V5: BCLK Falling Edge Ringback
V5: PICCLK Falling Edge Ringback
NOTES:
1. Unless otherwise noted, all specifications in this table apply to FC-PGA/FC-PGA2 processors frequencies
and cache sizes.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the V
This specification is an absolute value.
Figure 11. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins
Datasheet
T# Parameter
IL
IL
IH
IH
T3
V2
V1
®
Intel
Celeron
Min
Nom
Max
0.50
0.70
2.00
2.00
–0.58
3.18
2.00
2.00
0.50
0.70
(rising) or V
IH
V5
V3
T6
T4
®
Processor up to 1.10 GHz
Unit
Figure
Notes
V
11
V
11
V
11
V
11
V
11
V
11
2
V
11
2
V
11
2
V
11
2
(falling) voltage limits.
IL
V3
V4
T5
53
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