Intel CELERON 1.10 GHZ Datasheet page 125

Table 59. Alphabetical Signal Reference (Sheet 6 of 7)
Signal
SMI#
STPCLK#
TCK
TDI
TDO
TESTHI
(S.E.P.P. only)
THERMDN
THERMDP
THERMTRIP#
TMS
TRDY#
TRST#
V
CC 1.5
(PGA packages
only)
V
CC 2.5
(PGA packages
only)
V
CC CMOS
(PGA packages
only)
Datasheet
Type
The SMI# (System Management Interrupt) signal is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors save the
I current state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the bus and APIC units. The processor continues to snoop bus transactions
I
and may latch interrupts while in Stop-Grant state. When STPCLK# is deasserted,
the processor restarts its internal clock to all units, resumes execution, and services
any pending interrupt. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
The TCK (Test Clock) signal provides the clock input for the Intel Celeron processor
I
Test Access Port.
The TDI (Test Data In) signal transfers serial test data into the processor. TDI
I
provides the serial input needed for JTAG specification support.
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO
O
provides the serial output needed for JTAG specification support.
I Refer to Section 2.6 for implementation details.
O Thermal Diode p-n junction. Used to calculate core temperature. See
I Thermal Diode p-n junction. Used to calculate core temperature. See
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains latched,
and the processor stopped, until RESET# goes active. There is no hysteresis built
O
into the thermal sensor itself; as long as the die temperature drops below the trip
level, a RESET# pulse will reset the processor and execution will continue. If the
temperature has not dropped below the trip level, the processor will reassert
THERMTRIP# and remain stopped. The system designer should not act upon
THERMTRIP# until after the RESET# input is deasserted. Until this time, the
THERMTRIP# is indeterminate.
The TMS (Test Mode Select) signal is a JTAG specification support signal used by
I
debug tools.
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready
I to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all system bus agents.
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. Intel
I Celeron processors require this signal to be driven low during power on Reset. A
680 ohm resistor is the suggested value for a pull down resistor on TRST#.
The V pin provides the CMOS voltage for use by the platform. The 2.5 V
CC CMOS
must be provided to the V
I
The processor re-routes the 1.5 V input to the V
supply for V must be the same one used to supply V
CC 1.5
The V pin provides the CMOS voltage for use by the platform. The 2.5 V
CC CMOS
I must be provided to the V
The processor re-routes the 2.5 V input to the V
The V pin provides the CMOS voltage for use by the platform. The 2.5 V
CC CMOS
O
must be provided to the V
® ®
Intel Celeron Processor up to 1.10 GHz
Description
input and 1.5 V must be provided to the V
CC 2.5
CC CMOS
input and 1.5 V must be provided to the V
CC 2.5
CC CMOS
input and 1.5 V must be provided to the V
CC 2.5
Section 4.1.
Section 4.1.
input.
CC 1.5
output via the package. The
TT .
input.
CC 1.5
output via the package.
input.
CC 1.5
125