Intel CELERON 1.10 GHZ Datasheet page 123

Table 59. Alphabetical Signal Reference (Sheet 4 of 7)
Signal
LINT[1:0]
LOCK#
PICCLK
PICD[1:0]
PLL1, PLL2
(PGA packages
only)
PRDY#
PREQ#
PWRGOOD
Datasheet
Type
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all
APIC Bus agents, including all processors and the core logic or I/O APIC
component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those names
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®
on the Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all system bus agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction end of the last transaction.
I/O
When the priority agent asserts BPRI# to arbitrate for ownership of the system bus,
it will wait until it observes LOCK# deasserted. This enables symmetric agents to
retain ownership of the system bus throughout the bus locked operation and ensure
the atomicity of lock.
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or
I I/O APIC which is required for operation of all processors, core logic, and I/O APIC
components on the APIC bus.
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message passing
I/O on the APIC bus, and must connect the appropriate pins of the Intel Celeron
processor for proper initialization.
All Intel Celeron processors have internal analog PLL clock generators that require
quiet power supplies. PLL1 and PLL2 are inputs to the internal PLL and should be
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connected to V
CC CORE
platform design guide for implementation details.
The PRDY (Probe Ready) signal is a processor output used by debug tools to
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determine processor debug readiness.
The PREQ# (Probe Request) signal is used by debug tools to request debug
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operation of the processors.
The PWRGOOD (Power Good) signal is a 2.5 V tolerant processor input. The
processor requires this signal to be a clean indication that the clocks and power
supplies (V , etc.) are stable and within their specifications. Clean implies
CC CORE
that the signal will remain low (capable of sinking leakage current), without glitches,
from the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high (2.5 V) state.
Figure 43 illustrates the relationship of PWRGOOD to other system signals.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD. It must also meet the
minimum pulse width specification in
1 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
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internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
PWRGOOD Relationship at Power-On
BCLK
VCC ,
CORE
V
REF
PWRGOOD
RESET#
® ®
Intel Celeron Processor up to 1.10 GHz
Description
through a low-pass filter that minimizes jitter. See the
Table 17 and Table 18, and be followed by a
1 ms
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