Non-Agtl+ Signal Quality Specifications And Measurement Guidelines; Overshoot/Undershoot Guidelines; Non-Agtl+ Overshoot/Undershoot, Settling Limit, And Ringback - Intel CELERON 1.10 GHZ Datasheet

3.3 Non-AGTL+ Signal Quality Specifications and Measurement
Guidelines
There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot,
ringback, and settling limit. All three signal quality parameters are shown in
AGTL+ signal group.
Figure 14. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback
NOTES:
1. For the FC-PGA/FC-PGA2 packages, V
PWRGOOD. V
Section
3.3.1

Overshoot/Undershoot Guidelines

Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below V
due to the fast signal edge rates. (See
damaged by repeated overshoot events on the voltage tolerant buffers if the charge is large enough
(i.e., if the overshoot is great enough). The PPGA and S.E.P. packages have 2.5 V tolerant buffers
and the FC-PGA/FC-PGA2 packages has 1.5 V or 2.5 V tolerant buffers.
However, excessive ringback is the dominant detrimental system timing effect resulting from
overshoot/undershoot (i.e., violating the overshoot/undershoot guideline will make satisfying the
ringback specification difficult). The overshoot/undershoot guideline is 0.7 V for the PPGA
and S.E.P. packages and 0.3 V for the FC-PGA/FC-PGA2 packages and assumes the absence
of diodes on the input. These guidelines should be verified in simulations without the on-chip
ESD protection diodes present because the diodes will begin clamping the signals (2.5 V tolerant
signals for the S.E.P. and PPGA packages, and 2.5 V or 1.5 V tolerant signals for the FC-PGA/
FC-PGA2 packages) beginning at approximately 0.7 V above the appropriate supply and 0.7 V
below V
SS
should not rely on the diodes for overshoot/undershoot protection as this will negatively affect the
life of the components and make meeting the ringback specification very difficult.
Datasheet
Overshoot
V
HI
V
LO
V
SS
Time
= 2.5 V for BCLK, PICCLK, and PWRGOOD. BCLK and PICCLK signal quality is detailed in
HI
3.1.
. The overshoot/undershoot guideline limits transitions beyond V
SS
. If signals are not reaching the clamping voltage, this will not be an issue. A system
®
Intel Celeron
Rising-Edge
Ringback
Settling Limit
Undershoot
= 1.5 V for all non-AGTL+ signals except for BCLK, PICCLK, and
HI
Figure 14 for non-AGTL+ signals.) The processor can be
®
Processor up to 1.10 GHz
Figure 14 for the non-
Settling Limit
Falling-Edge
Ringback
or V
CC SS
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