System Bus Ac Specifications (Apic Clock And Apic I/O) At The Processor Core Pins (For S.e.p. And Pga Packages) - Intel CELERON 1.10 GHZ Datasheet

® ®
Intel Celeron Processor up to 1.10 GHz
Table 23. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core
Pins (For S.E.P. and PGA Packages)
T21: PICCLK Frequency
T22: PICCLK Period
T23: PICCLK High Time
• S.E.P.P and PPGA
• FC-PGA/FC-PGA2
T24: PICCLK Low Time
• S.E.P.P and PPGA
• FC-PGA/FC-PGA2
T25: PICCLK Rise Time
T26: PICCLK Fall Time
T27: PICD[1:0] Setup Time
• S.E.P.P and PPGA
• FC-PGA/FC-PGA2
T28: PICD[1:0] Hold Time
T29: PICD[1:0] Valid Delay (S.E.P.P
and PPGA only)
T29a: PICD[1:0] Valid Delay (Rising
Edge) (FC-PGA/FC-PGA2
only)
T29b: PICD[1:0] Valid Delay (Falling
Edge) (FC-PGA/FC-PGA2
only)
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
core pins. All APIC I/O signal timings are referenced at 1.25 V at the processor core pins.
4. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. Referenced to PICCLK rising edge.
6. For open drain signals, valid delay is synonymous with float delay.
7. Valid delay timings for these signals are specified to 2.5 V +5%.
8. Valid delay timings for these signals are specified to 1.5 V +5%.
44
T# Parameter Min Max Unit
2.0 33.3 MHz
30.0 500.0 ns
11.0 ns
10.5 ns
11.0 ns
10.5 ns
0.25 3.0 ns
0.25 3.0 ns
8.0 ns
5.0 ns
2.5 ns
1.5 10.0 ns
1.5 8.7 ns
1.5 12.0 ns
Figure Notes
3
3 @>2.0 V
3 @>1.7 V
3 @<0.5 V
3 @<0.7 V
3 (0.5 V–2.0 V)
3 (2.0 V–0.5 V)
5 5
5 5
5 5
4 5, 6, 7
4 5, 6, 8
4 5, 6, 8
Datasheet