System Bus Ac Specifications (Tap Connection) At The Processor Edge Fingers (For S.e - Intel CELERON 1.10 GHZ Datasheet

Table 24. System Bus AC Specifications (APIC Clock and APIC I/O)
T21: PICCLK Frequency
T22: PICCLK Period
T23: PICCLK High Time
T24: PICCLK Low Time
T25: PICCLK Rise Time
T26: PICCLK Fall Time
T27: PICD[1:0] Setup Time
T28: PICD[1:0] Hold Time
T29a: PICD[1:0] Valid Delay (Rising Edge)
T29b: PICD[1:0] Valid Delay (Falling Edge)
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
pins. All APIC I/O signal timings are referenced at 0.75 V at the processor pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150
Table 25. System Bus AC Specifications (TAP Connection) at the Processor Edge Fingers
(For S.E.P. Package)
T30': TCK Frequency
T31': TCK Period
T32': TCK High Time
T33': TCK Low Time
T34': TCK Rise Time
T35': TCK Fall Time
T36': TRST# Pulse Width
T37': TDI, TMS Setup Time
T38': TDI, TMS Hold Time
T39': TDO Valid Delay
T40': TDO Float Delay
T41': All Non-Test Outputs Valid Delay
T42': All Non-Test Inputs Setup Time
T43': All Non-Test Inputs Setup Time
T44': All Non-Test Inputs Hold Time
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel ® Celeron ® processor frequencies.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.70 V at the processor edge
fingers. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the processor edge fingers.
3. Not 100% tested. Specified by design characterization.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 2.5 V +5%.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
Datasheet
T# Parameter
T# Parameter
®
Intel Celeron
Min Max Unit
2.0 33.3 MHz
30.0 500.0
10.5
10.5
0.25 3.0
0.25 3.0
5.0
2.5
1.5 8.7
1.5 12.0
load pulled up to 1.5 V.
Min Max Unit
16.667 MHz
60.0 ns
25.0 ns
25.0 ns
5.0 ns
5.0 ns
40.0 ns
5.5 ns
14.5 ns
2.0 13.5 ns
28.5 ns
2.0 27.5 ns
27.5 ns
5.5 ns
14.5 ns
®
Processor up to 1.10 GHz
1, 2, 3
Figure Notes
ns 3
ns 3 @ > 1.7 V
ns 3 @ < 0.7 V
ns 3 (0.7 V–1.7 V)
ns 3 (1.7 V–0.7 V)
ns 5 4
ns 5 4
ns 3, 4 4, 5, 6
ns 3, 4 4, 5, 6
Figure Notes
3
3 @1.7 V
3 @0.7 V
3 (0.7 V–1.7 V)
3 (1.7 V–0.7 V)
6 Asynchronous
9 5
9 5
9 6, 7
9 6, 7
9 6, 8, 9
9 6, 8, 9
9 5, 8, 9
9 5, 8, 9
4
4
45