Phase Lock Loop (Pll) Power; Processor Decoupling; System Bus Agtl+ Decoupling; Package - Intel CELERON 1.10 GHZ Datasheet

The PPGA package has more power (88) and ground (80) pins than the S.E.P. Package. Of the
power pins, 77 are used for the processor core (V
voltage (V
processor compatibility.
FC-PGA/FC-PGA2 packages have 77 V
V , and one V
CC 2.5
cache. The V
The V
CC CMOS
a design, the V
Additionally, 2.5 V must be provided to the V
input. The processor routes the CMOS voltage level through the package that it is compatible with.
For example, processors requiring 1.5 V CMOS voltage levels route 1.5 V to the V
Each power signal, regardless of package, must meet the specifications stated in
addition, all V
connect to a system ground plane. In addition, the motherboard must implement the V
voltage island or large trace. Similarly, all V
2.3.1

Phase Lock Loop (PLL) Power

It is highly critical that phase lock loop power delivery to the processor meets Intel's requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL.
2.4

Processor Decoupling

Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. This causes voltages on
power planes to sag below their nominal values if bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in
of the component.
2.4.1

System Bus AGTL+ Decoupling

The S.E.P. Package and FC-PGA/FC-PGA2 packages contain high frequency decoupling
capacitance on the processor substrate, where the PPGA package does not. Therefore, Celeron
processors in the PGA packages require high frequency decoupling on the system motherboard.
Bulk decoupling must be provided on the motherboard for proper AGTL+ bus operation for all
packages. See AP-585, Pentium
587, Pentium
®
Pentium
Datasheet
). The other 3 power pins are V
REF
. V
CC CMOS CC CORE
inputs are used as the AGTL+ reference voltage for the processor.
REF
pin is provided as a feature for future processor support in a flexible design. In such
pin is used to provide the CMOS voltage for use by the platform.
CC CMOS
pins must be connected to a voltage island while all V
CC CORE
Table 5. Failure to do so can result in timing violations or a reduced lifetime
®
II Processor AGTL+ Guidelines (Order Number 243330), AP-
®
II Processor Power Distribution Guidelines (Order Number 243332), and the
II Processor Developer's Manual (Order Number 243502) for more information.
®
Intel Celeron
) and 8 are used as a AGTL+ reference
CC CORE
, V and V
CC 1.5 CC 2.5
, 77 ground pins, eight V
CC CORE
inputs supply the processor core, including the on-die L2
input and 1.5 V must be provided to the Vcc
CC 2.5
pins must be connected to a system ground plane.
SS
®
Processor up to 1.10 GHz
and are used for future
CC CMOS
, one V , one
REF CC 1.5
CC CMOS
Table 4. In
pins have to
SS
pins as a
TT
1.5
output.
19