Agtl+ System Bus Specifications; Processor Agtl+ Bus Specifications - Intel CELERON 1.10 GHZ Datasheet

2.11

AGTL+ System Bus Specifications

It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to V
between the ends of the signal traces and the V
approximate the substrate impedance. The valid high and low levels are determined by the input
buffers using a reference voltage called V
lengths are tightly controlled, see the Intel
or the Intel
Number 245088) for more information.
Table 8 below lists the nominal specification for the AGTL+ termination voltage (V
AGTL+ reference voltage (V
the processor core, but should be set to
the motherboard. It is important that the motherboard impedance be specified and held to:
•
±20% tolerance (S.E.E.P. and PPGA)
•
±15% tolerance (FC-PGA/FC-PGA2)
It is also important that the intrinsic trace capacitance for the AGTL+ signal group traces is known
and well-controlled. For more details on AGTL+, see the Pentium
Manual (Order Number 243502) and AP-585, Pentium
Number 243330).
Table 8. Processor AGTL+ Bus Specifications
Symbol
V
TT
R
TT
V
REF
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. V must be held to 1.5 V ± 9%; dI
TT
1.5 V ± 3% while the Intel Celeron processor system bus is idle. This is measured at the processor edge
fingers.
3. V is generated on the processor substrate to be
REF
created on the motherboard for processors in the PPGA package.
4. V and Vcc
TT
processor system bus is idle (static condition). This is measured at the PGA370 socket pins on the bottom
side of the baseboard.
5. The value of the on-die R
on-die R
details on the RTTCTRL signal. Refer to the recommendation guidelines for the specific chipset/processor
combination.
6. V is generated on the motherboard and should be 2/3 V
REF
V decoupling on the motherboard.
REF
Datasheet
at each end of the signal trace. These termination resistors are placed electrically
TT
® ®
Celeron Processor (PPGA) with the Intel
) is generated on the processor substrate (S.E.P. Package only) for
REF
Parameter
Bus Termination Voltage
• S.E.P.P and PPGA
• FC-PGA/FC-PGA2
Termination Resistor
• S.E.P.P and PPGA
• FC-PGA/FC-PGA2
(on die R )
TT
Bus Reference Voltage
• S.E.P.P and PPGA
• FC-PGA/FC-PGA2
CC VTT
must be held to 1.5V ±9%. It is required that V
1.5
is determined by the resistor value measured by the RTTCTRL signal pin. The
TT
tolerance is ±15% based on the RTTCTRL resistor pull-down of ±1%. See
TT
®
Intel Celeron
voltage supply and generally are chosen to
TT
. Single ended termination may be possible if trace
REF
®
440EX AGPset Design Guide (Order Number 290637)
®
440LX AGPset Design Guide (Order
2
/ V for other AGTL+ logic using a voltage divider on
TT
3
®
II Processor AGTL+ Guidelines (Order
Min Typ
1.365 1.50
1.50
56
40
2
/ V
TT
3
0.950 2/3 V
TT
/dt is specified in Table 5. It is recommended that V
2
/ V nominally with the S.E.P. package. It must be
TT
3
and Vcc
TT
±2% nominally. Insure that there is adequate
TT
®
Processor up to 1.10 GHz
). The
TT
®
II Processor Developer's
Max Units Notes
1.635 V 1.5 V ± 9%
V 4
± 5%
130 5
3
V ± 2%
1.05 V 6
be held to
TT
be held to 1.5 V ±3% while the
1.5
Section 7.0 for more
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