Recommended Connections For Unused Pins; System Bus Reset And Configuration Timings For Warm Reset; Connection For Unused Pins - Intel Itanium 2 Processor Datasheet
2 processor 1.66 ghz with 9 mb l3 cache / 1.66 ghz with 6 mb l3 cache / 1.6 ghz with 9 mb l3 cache / 1.6 ghz with 6 mb l3 cache/ 1.5 ghz with 6 mb l3 cache / 1.5 ghz with 4 mb l3 cache / 1.4 ghz with 4 mb l3 cache / 1.3 ghz with 3 mb l3 cache / 1.0 ghz wi
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Figure 2-7. System Bus Reset and Configuration Timings for Warm Reset
BCLK
PWRGOOD
RESET#
Bus Ratio
(A[21:17]#)
Additional
Configuration
Signals
2.8
Recommended Connections for Unused Pins
Pins that are unused in an application environment (as opposed to testing environment) should be
connected to the states listed in
such and do not have a recommended state for unused connection.
Table 2-26. Connection for Unused Pins (Sheet 1 of 2)
AGTL+ pins
HSTL Clock Signals
All Power Signals
PWRGOOD
TUNER[2:1]
TAP Signals
TCK
TRST#
TDI
TDO
TMS
Datasheet
T
C
T
= 1.15 ns minimum; (set up time to BCLK for deassertion edge of RESET#)
A
T
= 1 ms minimum for warm reset
B
T
= Bus ratio signals must be asserted no later than RESET#
C
T
= 2 BCLKs minimum, 3 BCLKs maximum
D
T
= 4 BCLKs minimum
E
T
= 2 BCLKs minimum, 3 BCLKs maximum
F
Table
Pins/Pin Groups
t
t
t
t
-4
-3
-2
-1
T
B
T
E
2-26. Pins that must be used in an application are stated as
Recommended
Connections
H
Must be used
Must be used
Must be used
Must be used
L
L
H
H
H
Electrical Specifications
t
t
t
t
0
1
2
3
T
A
T
D
T
F
000777b
Notes
1, 2
1, 3
1, 3
1, 3
1, 3
1, 3
35
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