Supermicro SuperServer SYS-122H-TN User Manual page 182

PCIe ACSCTL
Select Enabled to program ACS control to Chipset PCIe Root Port bridges. Select Disabled to
program ACS control to all PCIe Root Port bridges. The options are Enabled and Disabled.
PCIe Leaky Bucket Configuration Menu
►PCIe Leaky Bucket Configuration
Expected BER
This is the expected Bit Error Rate for all speeds. The default setting is 9687500000.
Time Window (Gen1/2)
This is the error burst protection time window for Gen1 and Gen2 speeds. A burst of errors
within the window is counted as one. The default setting is 65535.
Time Window (Gen3/4/5)
This is the error burst protection time window for Gen3, Gen4, and Gen5 speeds. A burst of
errors within the window is counted as one. The default setting is 2.
Error Threshold (Gen1/2)
This is the error threshold for Gen1 and Gen2 speeds. An event is triggered when the error
count exceeds the threshold. The default setting is 0.
Error Threshold (Gen3/4/5)
This is the error threshold for Gen3, Gen4, and Gen5 speeds. An event is triggered when the
error count exceeds the threshold. The default setting is 31.
Gen3/4/5 Re-Equalization
Select Enable to re-reun equalization only when operating at Gen3, Gen4, and Gen5 speeds.
The options are Enabled and Disabled.
Gen2 Link Degradation
Use this feature to enable PCIe Gen2 link degradation. Applies only when operating at PCIe
Gen2 speeds. The options are Disabled and Enabled.
Gen3 Link Degradation
Use this feature to enable PCIe Gen3 link degradation. Applies only when operating at PCIe
Gen3 speeds. The options are Disabled and Enabled.
Gen4 Link Degradation
Use this feature to enable PCIe Gen4 link degradation. Applies only when operating at PCIe
Gen4 speeds. The options are Disabled and Enabled.
SuperServer SYS-122H-TN: UEFI BIOS
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