Supermicro SuperServer SYS-122H-TN User Manual page 174

SuperServer SYS-122H-TN: UEFI BIOS
Leaky Bucket Low Bit
Use this feature to set the Low Bit value for the Leaky Bucket algorithm, which is used to check
the data transmissions between CPU sockets and the memory controller. The default setting is
12.
Leaky Bucket High Bit
Use this feature to set the High Bit value for the Leaky Bucket algorithm, which is used to check
the data transmissions between CPU sockets and the memory controller. The default setting is
13.
ADDDC Sparing (Available when populating 1Rx4, 2Rx4, and 4Rx4 DIMMs and when
"Memory PFA Support" is set to Disabled)
Select Enabled for Adaptive Double Device Data Correction (ADDDC) support, which will not
only provide memory error checking and correction but will also prevent the system from
issuing a performance penalty before a device fails. Please note that virtual lockstep mode will
only start to work for ADDDC after a faulty DRAM module is spared. The options are Disabled
and Enabled.
DDR PPR Type
Post Package Repair (PPR) is a new feature available for the DDR4/DDR5 technology. PPR
provides additional spare capacity within a DDR4/DDR5 DRAM module that is used to replace
faulty cell areas detected during system boot. PPR offers two types of memory repairs. Soft
Post Package Repair (sPPR) provides a quick, temporary fix on a raw element in a bank group
of a DDR4/DDR5 DRAM device, while hard Post Package Repair (hPPR) will take a longer
time to provide a permanent repair on a raw element. The options are PPR Disabled, Hard
PPR, and Soft PPR.
Note: This feature is available when "Memory PFA Support" is set to Disabled.
Enhanced PPR
Use this feature to set advanced memory test. Select Enabled to always execute for every
boot. The options are Disabled, Enabled, and Persistent.
Memory PFA Support (Available when the DCMS key is activated)
Select Enabled to enable memory Predictive Failure Analysis (PFA) support. PFA can be used
to avoid uncorrectable faults on the same memory page. The options are Disabled and
Enabled.
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