Group 1 Interface (Vi); Control Inputs (Cs, Ao, Wr, Rd); Scan Line Outputs/Return Line Inputs - Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement

CIRCUIT DESCRIPTION WJ-8718A/MFP
as additional entries are made. The
seven~character
frequency display is used to display the
threshold level, dwell time, and memory address only during numerical entry.
Wh~n
the
appropriate terminator key (see paragraph 2.4.4.2.1) is depressed, the number appears in the
appropriate display as described in paragraphs 2.4.4.4.3, 2.4.4.5.4, and 2.4.4.7.1. The
1.31)
signal
is generated by the timing circuits to blank the display during digit switching.
3.1.3.4
Group 1 Interface (Ul)
The VI interface scans the front panel switch matrix identified as Group 1, and
interfaces the associated LED indicators and displays. Refer to paragraph 3.1.2.2.1 for a
discussion of the switch matrix.
3.1.3.4.1
Ul Control Inputs (CS, AO, WR, RD)
The
VI
interface is addressed by the microprocessor at hexadecimal 1042 or 1043.
The address is latched by
V18
when the ALE signal goes low,
V19
is enabled, and the CS signal
(the Yl output of
V19)
goes low to enable VI. The level on the AO input to
VI
is established by
the LSB of the address. The microprocessor uses address 1042 (LSB = 0) if the information to be
transferred on the data bus is to be interpreted (by VI) as data. The address 1043 (LSB
=
1) is
used if the data bus word is to be interpreted as command or status. The WR signal goes low to
permit the microprocessor to load the bus with a word to be transmitted to VI; the word is
latched into
VI
when WR transitions high. The microprocessor sets RD low to request
information from VI. The VI data buffers load the information on the bus when RD is low and,
when RD transitions high, the information is latched by the microprocessor.
3.1.3.4.2
Ul Scan Line Outputs/Return Line Inputs
The internal circuits of
VI
provide a binary-coded count on the SLO through SL3
output lines. Three bits of the binary code (0 through 7) are decoded by U11 (described in
paragraph 3.1.3.5) to become the column scan lines (KCO through KC4). Each column scan line
is connected to one of the five X planes in the Group 1 switch matrix. Each switch in the
matrix is located at a point where the X and Y planes cross and can be identified by the unique
position it occupies. The Y planes of the matrix are connected to the return lines (RLO through
RL3) of VI. When a switch is closed, a circuit is completed from the column scan line, through
the closed switch, and through the return (row scan) line back to VI. The closed switch position
is coded and stored in
VI
RAM. During the execution of its program, the microprocessor
initiates any further action necessary to incorporate the functions of the closed switch.
The binary count (0 through 15) on the SLO through SL3 lines is applied to
multiplexer U4, where one of 16 channels is switched as the count proceeds (refer to paragraph
3.1.3.6). The selected channel output goes high, resulting in (through V5 or U6) a negative
cathode voltage to a front panel LED indicator or display array (see paragraphs 3.1.2.2.3 and
3.1.2.2.4). The LED is not forward biased and does not illuminate, unless its anode is
sufficiently more positive than the cathode. The anode drive is provided through the BO through
B3 outputs of VI, described in paragraph 3.1.3.4.3.
3-12