Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement page 85

Microprocessor front panel option
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CIRCUIT DESCRIPTION
WJ-8718A/MFP
3.2.4.3.4
Standby Mode
The EPROM devices are in reduced power standby mode when the CE enable lines
are held at TTL high logic level. During the standby mode, the outputs are in a high impedance
state, independent of the OE input, allowing the shared data bus to be driven by other devices
addressed for a read operation.
3.2.4.4
Random Access Memory (U3)
The Synthesizer Interface Board houses a single addressable read/write memory
device, consisting of a 16,384 (2K x 8) CMOS RAM integrated circuit, (U3). RAM stores data,
current receiver status, and serves as a stack for the temporary storage of the microprocessor's
internal registers during a program interrupt. Refer to Table 3-7 RAM/EPROM Address Data
for the binary equivalent addresses of the various chips.
3.2.4.4.1
RAM Operation
Power required for the operation of RAM U3 is +5 Vdc. The modes of operation
consist of read, write, high-Z, and low power.
3.2.4.4.2
Control Input
The
CE
input from decoder U7 goes low when the hexadecimal address on the
microprocessor data bus is in the range of 2000 through 27FF.
The read and write inputs are connected to the microprocessor RD and WR bus
control signals and are active (low) for their respective bus cycles.
3.2.4.4.3
Read Mode
When the decoded address is in the 2000 to 27FF range and the microprocessor
initiates a read operation, all bus cycles are identical to the read operation previously described
for EPROM (see paragraph 3.2.4.3.3).
3.2.4.4.4
Write Mode
When the decoded address is in the range of 2000 to 27FF and the microprocessor
initiates a write operation, decoder U7 output Y2 becomes active (low) and enables U3 address
inputs AD-AlO. During the data portion of the bus cycle, WR line becomes active (low) and a
rising edge of WR causes data to be written into the internal address selected by AD-AlO.
3.2.4.4.5
High-Z Mode
Any microprocessor bus cycle that does not enable Ul, U2, or U3 leaves all outputs
in a high-Z (high impedance) state. This disables the devices from having any effect on the bus.
3-30

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