Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement page 103

CIRCUIT DESCRIPTION WJ-8718A/MFP
3.3.1.6.6
Clock Input
A clock pulse is generated by the RC time constant of Rl and Cl and applied to
the clock input. The time constant, coordinated with the feedback and inversion characteristics
of V8B and F, provides square wave pulses of 1 MHz to a time delay generator internal to VI.
3.3.1.6.7
Transmit/Receive Control Lines
The TR/l signal is generated by
VI
to control the operation of the external
transceivers,
V2
and
V3
(paragraph 3.3.1.5). The TR/1 signal is set high to indicate output to
the 488 bus. Data/signals are on the DID! through DID8, EOI and DA V lines. Input (bus to
VI)
signals are on the NRFD and NDAC lines. TheTR/l signal is set low to indicate input signals
on the DI01 through DI08, EOI and DAV lines, and output signals on the NRFD and NDAC lines.
The TR/2 line is not used.
3.3.1.7
Master/Slave
Hand Off (U9, UI0)
When the receiver is programmed as a master device, it is necessary to control the
ATN bus signal for sending com mands over the bus. Register
V10
is used to control the DC
input of transceiver U3. The DC input determines the direction of the ATN transceiver.
To send a com mand out over the bus, the V10 register Q output is set to a low
state to reverse the control of the ATN transceiver channel. By enabling its driver, the ATN
input is then held low by R7 which sets ATN active on the GPIB. With ATN active, any data
sent through the
V2
data buffers is treated as a command instruction by any device connected
to the master receiver. Resistors R5 and R6 keep REN and SRQ inactive, while the DC input is
in the com mand state.
When address 1060 is placed on the bus and latched by U6, decoder U7 output is
then enabled. During a WR bus cycle, the V9D output goes low. On the low-to-high transition
at the end of the WR cycle, the data (from ADO) on the D input of latch V10 is clocked into the
Q
output.
The U10
Q
output is low during normal operation, allowing the normal ATN signal
from V3 to be passed through V9B to VI.
V10 is reset on power-up by the inverted reset signal from V8D.
3.4 232M OPTION CIRCUIT DESCRIPTION
3.4.1 TYPE 796037 (ASYNCHRONOUS) I/O INTERFACE BOARD (232M-A3)
The (Asynchronous) I/O Interface Board (232M-A3), when installed in an MFP
equipped receiver, interfaces the microprocessor in the MFP Option with the remote control
equipment. Figure
6-17
is the 232M-A3 schematic diagram.
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