Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement page 101

TABLE 3-22 WJ-8718A/MFP
TABLE 3-23
3.3.1.6.1 Read/Write Registers
The GPIB Interface structure includes eight registers that the microprocessor
writes to, and eight registers that the processor reads from. One read register and one write
register are used for the transfer of data. The remaining write registers are used by the
microprocessor to establish operating characteristics of VI. The remaining read registers
provide the processor with a monitor of bus and controller conditions.
The registers are accessed by the levels on the CS, RD, WR, and RSO through RS2
lines as listed in Table 3-22. Table 3-23 lists the RSO through RS2 codes and functions of the
read/write registers. The RSO through RS2 codes are established by the three least significant
bits of the address on the microprocessor bus lines. The
CS
signal level is established by
decoding other address bits, as described in paragraphs 3.3.1.1 and 3.3.1.2. The CS signal goes
low to enable V1 when a hexadecimal address between 1028 and 102F (Table 3-21) has been
placed on the bus and latched by the ALE signal. The RD or WR signal is activated when the
processor initiates a read or write operation to the addressed VI register.
Table 3-22. Read/Write Register Address Codes
Register
CS RD WR RSO - RS2
All read registers 0
0
1 Register Select Code
All write registers
0
1 0 Register Select Code
Don't care
1 x x xxx
Table 3-23. Register Select Codes
Read Registers RS2 RS1 RSO
Write Registers
Data-In 0 0 0
Data-Out
Interrupt Status 1 0 0
1
Interrupt Mask 1
Interrupt Status 2 0
1
0 Interrupt Mask 2
Serial Poll Status 0 1
1
Serial Poll Mode
Address Status 1
0
0
Address Mode
Command Pass Through
1 0 1
Auxiliary Mode
Address 0 1 1 0 Address 0/1
Address 1
1 1
1
EOS
The data-in register is used to move data from the 488 bus to the microprocessor in
the receiver control block when the receiver is addressed to listen. The data-out register is
used to move data onto the 488 bus. The GPIB Interface
(V1)
handles and initiates the required
handshake protocol.
The write interrupt mask registers are configured by the microprocessor to select
the events that will cause an interrupt signal to be generated by the corresponding bit in the
interrupt status registers. The status registers are read by the microprocessor to determine
which event has occurred so that the proper service routine can be executed.
3-46