Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement page 13

WJ-8718A/MFP
TABLE OF CONTENTS (Cont'd)
SECTION ill
CIRCUIT DESCRIPTION (Cont'd)
CONTENTS
Paragraph
3.2.4.8
3.2.5
3.2.5.1
3.2.5.2
3.2.5.3
3.2.5.4
3.2.5.5
3.2.5.6
3.2.5.7
3.2.5.8
3.2.5.9
3.2.5.10
3.2.5.11
3.2.5.12
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.1.2.1
3.3.1.2.2
3.3.1.3
3.3.1.4
3.3.1.5
3.3.1.6
3.3.1.6.1
3.3.1.6.2
3.3.1.6.3
3.3.1.6.4
3.3.1.6.5
3.3.1.6.6
3.3.1.6.7
3.3.1. 7
3.4
3.4.1
3.4.1.1
3.4.1.2
3.4.1.2.1
3.4.1.2.2
3.4.1.3
3.4.1.4
3.4.1.5
Frequency Registers
(V12-
U17) •.•....•........•.......•..............
Type 794308-2 IF Interface (MFP-A3) ......•...........................
Bidirectional Bus Transceiver (U20) .
Address Latch (U 8) .
Decoder Select (U11) ..••............................................
RF Gain Conversion D/A
(V23) • •••••.•••••••••••••••••••••••••••••••••
Audio/Gain Switch
(V22) ••••.••.•.•••••••••••••••.•••••••••.•••••...•
Registers (U5, U9,
V21) •••••••..•••.•••••••.•.•••••.•••••••••••.•••.•
Bandwidth, BFO Inhibit, and AGC Dump (U5) .
Gain/Detector Mode
(V9) ••••••.•••••••••••••••••.•.•••.••••••••••••.
Local/Remote Select (U21B) .
Audio On/Off (U21A, U16A, U16B) .
A/D Converter (U2 5) .
Analog Inputs .
488M Option Circuit Description .
Type 796075 I/O Interface (488M-A3) .
Address Latch
(V
6) ........................•.........................
Address Decoder (U7) ...............................•................
U7 Enable ...........................................•..............
U7 Select ...................................•.." .
Switch Assembly (Sl) ....................•...•...•..................•
Tri-State Buffer/Inverter (U4) ................•.....•.................
Transceiver Network (U2 and U3) .........•.•...•.....................
GPIB (General Purpose Interface Bus),
(V1) ••••••••••••••••••••••••.••••
Read/Write Registers .•...............•......••....•......•.....•....
Reset Procedure ............•......•....•.•.•........•..............
488 Handshake and Management Signals ...........••............•......
Direct Memory Access (DMA) .....•....•.••....•.•.•..........•.•....
Data Ports ' .
Clock Input ............•...............•••.•..•.....•..........••..
Transmit/Receive Control Lines ................•.•......•.•••...•....
Master/Slave Hand Off
(V9,
U10) ..•...•....••..••....•...•..•..•.•....
232M Option Circuit Description .••....•...•..•....••..........•...•.•
Type 796037 (Asynchronous) I/O Interface Board (232M-A3) ...••...••.....
Address Latch
(V
2) ...•..•....•..........•..•.........•...•.•..••....
Address Decoder (V 4) •......•.....•....•.••.•.••......•.......••.....
U4 Enable ~ .
U 4 Select .
Switch Assembly (S2) ...•.•..••..•....•.••.•.•.•.•.•..•.•......•....•
Tri-State Buffer/Inverter
(V3) ••••••••••••••••••••••••••••••••••••••••
Baud Rate Network (V5, Sl) ••..•..•..•..••..•.....•.•....•..•....•...
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