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TABLE 3-6
WJ-8718A/MFP
Table 3-6. U17 Truth Table
Inputs
Output
Clear
Clock
G1
G2
D
Q
H
X
X
X
X
L
*L
L
X
X
X
QO
*L
H
X
X
QO
*L
X
H
X
QO
L
L
L
L
L
L
L
L
H
H
*
Denotes a steady-state condition.
NOTES:
1.
QO denotes level of Q before the steady-state condition
was established.
2.
When either ODI or OD2 is high, the output is disabled
to the high-impedance state; however, sequential oper-
ation of the flip-flop is not affected.
In summary, the U17 outputs (Ql and Q2) reflect the data on the Dl and D2 inputs
when the microprocessor addresses U17 at address 1040 and initiates a read operation. The Dl
input is tied to
+5
Vdc and, therefore, is always high. This high level will be clocked to the Ql
output the first time the clock (CLK) input transitions high and Q1 will remain high until U17 is
reset (clear high); a high level at Ql is evidence that the clock has transitioned high. The clock
input is the inverted (by 21C) clock output of optical encoder MFP-A2Ul, described in
.
par~aph
3.1.1.1.
The optical encoder converts the rotation of the front panel tuning wheel into
electrical pulses, and outputs two trains of square wave pulses (on the clock and direct lines)
which are applied to the Front Panel Encode Board at pins B19 and B20 of XAIB. The trains of
pulses are phase-related to the direction of tuning wheel rotation;
DIR
leads clock if the
rotation is clockwise, as shown in Figure
3-4,
and lags clock if the rotation is counterclockwise,
as shown in Figure 3-5.
The Ql output of U17 is high only when clock transitions high; clock transitions
high only when the front panel tuning wheel is rotated (and clear is low). The microprocessor
addresses U17 for a read operation approximately every
5
milliseconds during the execution of
its program and "looks at" the Ql output (on the LSB of the data bus).
If Ql is low, the
processor knows that the tuning wheel is not being rotated and continues with the execution of
its program.
If the microprocessor finds that Q1 is high, the tuning wheel is being rotated and
the processor examines the Q2 output (on the ADI data bus line) to determine the direction of
rotation. At the same time the positive clock transition transferred the Dl input level to Ql,
the D2 input level transferred to Q2. D2 is the inverted (by U21E)
DIR
line pulse train from the
optical encoder. Figures 3-4 and 3-5 illustrate the timing for the clockwise and counterclock-
wise rotation of the tuning wheel. If the direction is clockwise, the D2 input is high each time
the U17 clock transitions high; therefore, Q2 will go high (if it was low at the first
3-18
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