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CIRCUIT DESCRIPTION
WJ-8718A/MFP
The microprocessor has a special way of handling subroutines in order to ensure an
orderly return to the main program.
When the processor receives a call instruction, it
increments the program counter and stores the counter's contents in
a
reserved area in RAM on
the MFP-A4 board. This memory area is called a stack. The stack saves the address of the
instruction to be executed after the subroutine is completed.
Next, the processor loads the
subroutine address in its program counter, ensuring that the next instruction fetched will be the
first step of the subroutine.
The last step of a subroutine is a return.
After the processor fetches a return
instruction, it replaces the current contents of the program counter with the address on the top
of the stack and the program is resumed at the point immediately following the original call
instruction.
The processor uses an area of RAM as a stack and maintains an internal pointer
register which contains the address of the most recent stack entry. The external stack allows
subroutine "nesting", a procedure during which one subroutine calls a second routine.
3.2.3.1.2
Instruction Register and Decoder
Each operation that the microprocessor can perform is identified by a unique byte
of data known as an instruction or operation code, generally referred to as an opcode. An 8-bit
binary-coded word used as an opcode can distinguish between 256 (2 8 ) alternative actions.
The microprocessor fetches an instruction from memory (EPROM) in two distinct
operations.
First, the processor transmits the address in its program counter to the memory.
Next, mem ory returns the addressed byte to the processor. The instruction byte is stored in a
circuit within the processor called the instruction register and is used to direct the activities of
the processor during the instruction execution.
The eight bits stored in the instruction register are decoded in the instruction
decoder and machine cycle encoding network (Figure 3-6) and are used to activate the output
lines of the decoder. The enabled lines are gated by timing signals in the timing and control
block to develop electrical signals that initiate specific actions in the processor registers, AL U,
and buffers. The outputs of the instruction decoder and internal clock generator provide the
state and machine cycle timing signals (paragraph 3.2.3.2).
An 8-bit instruction may not always be sufficient to specify a particular processing
action. If more than one byte is used for an instruction, successive instruction bytes are stored
in sequentially adjacent memory locations. The microprocessor performs more than one fetch
in succession to obtain the full instruction. The first byte retrieved from memory is placed in
the instruction register while subsequent bytes are placed in temporary storage internal to the
processor. The processor then proceeds with the execution phase.
3.2.3.1.3
Arithmetic Logic Unit (ALU) and Flag Register
The ALU is the portion of· the microprocessor hardware which performs the
arithmetic and logic operations on the binary data and is inaccessible to the programmer. (An
example of the use of the ALU is when the program counter is incremented.)
3-22
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