Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement page 133

TABLE 4-14
TABLE 4-15
Table 4-14. Front Panel Encode Support Circuits (Cont'd)
WJ-8718A/MFP
Support Circuit Supports Function
U15A VI, U2
RESET buffer
U15B V19 Address decode for U19
U15C VI, U2, U17 RD buffer
V15D VI,
U2, UI6 WR buffer
UI6A NV
UI6B NV
U16C NU
UI6D
V20 CLK decode
U2IA NV
U21B
NU
V21C U7
Tuning wheel CLK inverter
V21D V17
CLR inverter
V21E U17 Tuning wheel DIR inverter
U21F NV
NOTE: NV
denotes not used
4.1.4.5
Optional Asynchronous I/O Board Modules (232M-A3)
The Asynchronous I/O Board (optional) is primarily responsible for the transfer of
data between equipment via the RS-232/C interface. Troubleshooting is required when the
receiver appears inoperative during remote operation only. The card contains two modules to
support the microprocessor system. All pertinent information for the modules is given in
Tables 4-15 and 4-16. The tables are to be used in conjunction with the information given in
paragraph 4.1.4.5.1.
Table 4-15. Asynchronous I/O Board Modules (232M-A3)
Module
Data 1
2
Description
Receiver address/
USART
parity/master
slave switch
Functional Circuit S2
VI
Tri-State Buffer U3
Internal (Ul)
Buffer Clock U4, pin 14 U4, pin 15
Data Capture Latch NA NA
Data Capture Clock NA NA
Address Capture Latch U2 U2
Address Capture Clock V6B, pin 6
U6B, pin 6
Address Decode U4 U4
NOTE: NA indicates not applicable.
4-22