Rd Timing Diagram - Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement

WJ-8718A/MFP
FIGURE 3-7
,,-----------.-;/
(ALE), during the first clock state of each machine cycle. After the eight address bits have
been latched, the processor initiates either a read or write operation by providing a low l-evel on
the RD or WR control line.
Figure 3-7 illustrates the timing of a read cycle. A low level on the
RD
line
enables the addressed memory device and, after a period of time (the access time of the
memory), valid data will be present on the ADO through AD7 lines. The processor next loads
the data into its instruction register (paragraph 3.2.3.1.2) and raises RD high, disabling the
addressed memory device.
After ALE drops, a low level on the WR line causes data to be placed on the ADO
through AD7 lines by the processor. The data is loaded into the addressed memory when WR
goes high. Figure 3-8 illustrates a write timing pulse.
The A8 through A15 data lines are used to identify the MSBs of a memory or I/O
location for a data transfer cycle. Selected bits provide enabling pulses to addr·ess decode
circuits which, in turn, provide enabling pulses to read-only and write-only registers on the
MFP-Al, A3, and A4 boards, and, if the 232M or 488M Option is in use, on the 232M-A3 or
488M-A3 boards.
A8- AI5 _ _
~X,_
V_A_L_I D_A_D_D_R_E_S_S
~X'_
_
ADO-AD7 - -
--<
Ao-A7
)--<
>-<
00-07
>---< _
A L E J
RD - - - - - - , , - - - -_ _
---J/
Figure 3-7. RD Timing Diagram
3.2.3.5
Reset In/Reset Out
The microprocessor is reset when the RESET IN line is low and commences
execution of its program when the line goes high. The RESET OUT line goes high to reset the
MFP-Al display interface circuits and, if the 232M or 488M Option is in use, the 232M-A3 or
488M-A3 I/O port.
3-25