Addresses 1010 Through 1017 - Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement

TABLE 3-13
Table 3-13. Addresses 1010 through 1017
WJ-8718A/MFP
Address Bit
23 2 2 2 1 2 0 23 22 2 1 2 0
2
3 2 2
2
1 2 0 23 2 2 2 1 2 0
Data Line 15 14 13 12 11 10 9 8 7 6 5
4
3 2
1 0
U21B
0 0 0 1
0 0 0
0 0 0 0
1 0 0 0
0
U5
0 0 0
1
0
0 0 0 0 0 0 1
0
0 0 1
U9 0
0
0
1 0 0 0 0 0 0 0
1
0
0 1
0
U23 0 0 0 1 0 0 0 0 0
0
0 1
0 0 1 1
U25
0 0
0
1 0 0 0 0 0 0 0
1 0 1 0 0
U16, U6
*
0 0 0 1 0 0 0 0 0 0 0 1
0 1 0 1
U7*
0 0 0
1
0
0
0
0 0 0 0 1 0
1 1 0
U21A
0 0 0 1 0
0 0 0 0 0
0
1 0
1 1 1
* Unused in this application
3.2.5.2
Address Latch (U8)
The data' on the inputs to U8 contain the low order address portion of the bus cycle
from Transceiver U20. When ALE goes low, indicating a valid address on the bus, this signal is
inverted by UI0B. The resultant positive-going edge when applied to the clock input of U8
latches the data into the
Q
outputs. These outputs remain in this state until the next ALE
cycle. This demultiplexes the address from the data portion of ADO-AD7 low order lines.
3.2.5.3
Decoder Select (U11)
The select inputs to U11 (AO, AI, and A2) are the three least significant bits of the
address latched by U8. As shown in Table 3-14 , a Y output goes low only when Ull is enabled
and a particular 3-bit code is on the select inputs. Comparison of the select input codes listed
in Table 3-14, with the three least significant bits of the addresses listed in Table 3-13, shows
that one of the YO through Y7 outputs goes low when one of the addresses in the
hexadecimal 1010 through 1017 range is on the bus. Each Y output is tied to an enable input of
a read-only device or the clock input of a write-only device on the IF Interface Board
(MFP-A3).
When U11 is enabled, the Y output goes low during the time that the RD or WR
signal is low. If the RD signal enables Ull, the addressed device is a tri-state buffer (unused in
this application) which is enabled by the low pulse from a U7 output. However, if the WR signal
enables U7, the resultant high-to-Iow level from U7 to the clock input of the addressed device
3-36