Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement page 79

CIRCUIT DESCRIPTION WJ-8718A/MFP
The flag-bit register is associated with the ALU and the accumulator. The flag-
bits specify certain conditions that occur during the course of arithmetic and logical
manipulations. The five Intel 8085A Microprocessor flag-bits are carry, auxiliary, sign, zero,
and parity. The bits are important to the programmer in establishing the control of processor
operation. .
3.2.3.2
Internal Clock Generator and Timing
The activities of the microprocessor are cyclical. The processor fetches an
instruction, performs the required operations, fetches the next instruction, and so on. This
orderly sequence of events requires precise timing. Timing is provided by an external
oscillator.
The combined fetch and execution of a single instruction is referred to as an
instruction cycle and consists of a series of machine cycles, whose nature is determined by the
opcode. The opcode is accessed in the first machine cycle of an instruction cycle. Each·
machine cycle consists of a series of clock, or timing, cycles determined by the type of
instruction being executed and the machine cycle within the instruction cycle.
3.2.3.3
Interrupt Control
To the microprocessor, an interrupt signal is similar to a subroutine call except
that it is initiated externally rather than by the program. If an optional remote interface has
been installed, a high level on an interrupt line (RST 5.5 or RST 6.5) is generated by the I/O port
on the I/O Interface Board (488M-A3 or 232M-A3) when a data word has been received from or
requested by the controller. An interrupt request sets a processor interrupt enable flip-flop;
the processor acknowledges the interrupt by suspending the execution of the main program and
automatically branches to a subroutine to service the interrupt. The status of the main
program is stored on the stack in RAM (paragraph 3.2.3.1.1) until the processor finishes the
interrupt service and returns to the main program.
3.2.3.4 Data Bus Control Lines
(RD, WIt,
ALE)
At the beginning of a fetch machine cycle, the processor places the contents of the
program counter (a memory address) on the 16-bit address bus. The high-order byte of address
data is placed on the A8 through A16 lines and will remain there for several clock cycles. The
low-order byte is placed on the ADO through AD7 lines and the microprocessor line drivers are
enabled. Unlike the upper address lines, the information on the lower address lines will remain
there for only one clock cycle after which the drivers will go to their high-impedance state.
This is necessary because the ADO through AD7 lines are multiplexed between the address and
data. During the first clock cycle of a machine cycle, ADO through AD7 output the eight
lowest bits of the address, after which the lines either output the desired data for a write
operation or the drivers will float, allowing the external device to drive the lines for a read
operation.
The address information on the ADO through AD7 lines is transitory, therefore, it
must be latched into selected external 8-bit latches. To facilitate the latching of the lowest
eight bits of data, the microprocessor provides a special timing signal, Address Latch Enable
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