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CIRCUIT DESCRIPTION
WJ-8718A/MFP
IN3, the audio monitoring circuit, creates a DC level from the audio for the A/D to
convert. Resistor R19 provides isolation; C22 couples the AC; CRI and CR2 half-wave rectify;
and C14, R21, and R20 integrate the signal to make it an input level for the A/D.
IN4
9
the 1st LO tuning voltage input is tested to see if the first local oscillator
synthesizer is locked.
If
unlocked, an error condition will occur in testing. Resistor R18 helps
to pull down the tested voltage.
IN5 is the test point for the -15 V power supply. Voltage dividers R14 and R15
provide a positive reference, while CR3 protects the point from going negative at the input of
the A/D.
IN6 is the test point for the +15 V power supply.
Voltage dividers R16 and R17
provide a positive reference to the input of the
AID.
IN7 is the test point for the 2nd LO tuning voltage.
No signal conditioning is
necessary.
3.3
488M OPTION CIRCUIT DESCRIPTION
3.3.1
TYPE 796075 I/O INTERFACE (488M-A3)
The 488M - A3 board interfaces the microprocessor in the interface section of the
MFP Option with the remote control equipment. All board components are powered by +5 Vdc,
applied across bypass capacitors C2 through C5.
Refer to Figure 6-7, Type 796075 I/O
Interface.
3.3.1.1
Address Latch (U6)
Integrated circuit U6 is an octal D-Type flip-flop. The clear (CLR) input is held
high by Vcc, causing information at the D inputs to be latched to the
Q
outputs on the positive-
going edge of the clock pulse. The clock pulse to U6 is the microprocessor control line ALE,
inverted by U8E. ALE goes low, and is inverted when a valid address has been placed on the
data bus. The resultant positive-going clock pulse to
V6
latches the lower-order address bits to
the Q outputs. From the outputs of U6, four of the address bits are decoded as necessary to
clock or enable the addressable circuits on the I/O board:
VI,
discussed in paragraph 3.3.1.6,
and U4, discussed in paragraph 3.3.1.4.
The three least significant bits of the address are
described in paragraph 3.3.1.6.1.
3.3.1.2
Address Decoder (U7)
Integrated circuit U7 is a three-to-eight line decoder, enabled by one high and two
low logic levels on the
G
inputs, as shown in Table 3-20. When U7 is enabled, the three select
inputs at A, B, and C are decoded and one of the eight outputs goes low.
3-42
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