Table of Contents
Advertisement
WJ-8718A/MFP
TABLE 3-,24
The majority of board components are powered by +5 Vdc, applied across bypass
capacitors C1, C6, C7 and C8. The zener voltage reference circuit, formed by VR1, VR2, R1,
R2, and C2 through C5, provides potentials of +12 and -12 Vdc for the U7 and US logic gates
and +12 Vdc for the baud rate generator, U5.
3.4.1.1
Address Latch (U2)
Integrated circuit U2 is an octal D-,Type flip-flop.
The output enable input is
grounded, causing information at the D inputs to be latched to the Q outputs on the positive-
going edge of the clock pulse. The clock pulse to U2 is the microprocessor control line ALE,
inverted by U6B. ALE goes low (and is inverted), when a valid address has been placed on the
data bus. The resultant positive-going clock pulse to U2 latches the lower-order address bits to
the
Q
outputs (Q6 and Q7 are unused). From the outputs of U2, five of the address bits
are
decoded as necessary to clock or enable the two addressable circuits on the I/O board:
UI,
discussed in paragraph
3.4~1.
7, and U3, discussed in paragraph 3.4.1.4. The LSB of the address is
described in paragraph 3.4.1.
7.5.
3.4.1.2
Address Decoder (U4)
U4 is a three-to-eight line decoder, enabled by one high and two low logic levels on
the G inputs, as shown in Table 3-24. When U4 is enabled, the three select inputs at
A,
B, and
C are decoded and one of the eight outputs goes low. In this application, only two outputs,
YO
and Y1, are used.
3.4.1.2.1
U4 Enable
The G1 enable input to U4 is the bit that is carried on the A12 data line.
Table
3-25
lists the addressable devices on the I/O board. The A12 bit is high when the least
significant bit of the MSD of the hexadecimal address is 1 (0001). G2B is the inverted (by U6A)
level of the AD5 addresss bit. To provide the two low levels to enable U4, AD5 must be high
and AD4 must be low. As shown in Table 3-25, the enabling conditions exist when one of the
hexadecimal addresses 1020, 1021, or 1022 has been plac,ed on the data bus.
Table 3-24. U4 Truth Table
Inputs
Outputs
Enable
Select
Gl
G2A
G2B
A
B
C
YO
Yl
H
L
L
L
L
L
L
H
H
L
L
L
L
H
H
L
3-49
Advertisement
Chapters
Table of Contents
