Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement page 86

WJ-8718A/MFP CIRCUIT DESCRIPTION
3.2.4.4.6
Low Power Mode
RAM U3, being CMOS, can be kept powered on to maintain all data stored in the
memory by holding Vcc/Vdd and CE to a 2 V level. Buffer VIODprovides isolation for CE with
power off; its open collector output is pulled up by R14.
3.2.4.4.7 Battery Backup
An inherent quality of RAM is that it is volatile, meaning that data is not retained
when power is removed. To prevent the loss of data, a battery (BTl) is used to power the RAMs
when power is down.
Transistor Ql, forward biased by Vcc when power is on, charges the 2.4 V battery
through R4 and R5. When power is down, Vcc drops to zero and the transistor becomes reverse
biased, allowing current to flow only to the RAM circuits connected to Vdd.
3.2.4.5
Bidirectional Bus Transceiver (U4)
Transceiver (U4) is made up of 16 high-speed CMOS buffer drivers, only eight of
which are enabled at the same time. The direction of the data (or which eight buffers are
enabled) is controlled by the DIR input and is connected to the RD line of the microprocessor
through NAND gate U9D. NAND gate U9Ds INTA input is not used in this design. When RD is
active (low), the eight buffers are enabled to allow bus data to be input to the microprocessor.
The rest of the time these buffers are tri-state. The opposite buffers are then enabled to allow
data to be output from the microprocessor to the bus.
3.2.4.6
Address Latch (U5, U6)
High-speed CMOS U5 and V6 are octal D-type flip-flops. The data on the inputs of
U5 and U6 contain the low-order and high-order address portion of the bus cycle. When ALE
goes low indicating a valid address on the bus, this signal is inverted by U9C. The resultant
positive-going edge, when applied to the clock inputs of U5 and U6, clocks the D inputs to the
Q
outputs. These outputs remain in this state until the next bus ALE cycle. This demultiplexes
the address from the data portion of ADO-AD7 (low-order) lines and provides a bus cycle of
equal duration on the A8...:A15 (high-order) bus address lines. The EN input is tied to the HLDA
output of the microprocessor and is not used in this design.
3.2.4.7
Address Decoders (U7, U8)
Table 3-8 is a truth table for U7, the high-order address decode operation, and
Table 3-9 is the truth table for the low-order address decode operation. When enabled by
applying a high to input G1 and a low to inputs G2A and G2B, these decoders provide a low logic
level on one of seven Y outputs.
The U7 inputs are the most significant four bits of the address bus A12 through
A15. A15 must always be low in order for either of these devices to be enabled. U7 outputs,
YO- Y4, are enabled for ROM1, U8 enables G2B (necessary for frequency and BFO data latch
strobes), RAM, and ROM2.
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