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CIRCUIT DESCRIPTION
WJ-8718A/MFP
3.1.3.13
Display Driver (U7)
Display driver U7 functions identically to U3, described in paragraph 3.1.3.8. The
outputs of U7 drive the receiver and memory address displays and the LED indicators associated
with the Group 2 switch matrix, described in paragraph 3.1.2.2.2.
3.1.3.14
Data Latch (U20)
U20 is an octal D-type flip-flop. The CLR input is tied high, allowing data at the
D inputs to transfer to the Q outputs when the clock (CLK) input transitions to a high.
During
the time clock remains at either a high or low level, the changes at the D inputs have no effect
on the Q outputs.
The clock input to U20 is the output from U16, configured to provide an OR
function. The active low signals on the U16 inputs are the Y3 output of U19 and the AND gate
U15 output.
In paragraph 3.1.3.2.2, it was established that U19Y3 goes low only when the
address 1046 has been on the bus and latched by U18. The AND gate (UI5) is configured (pin 12
tied high) so that the output follows the level of the WR signal. In summary, the clock signal to
U20 transitions high only when the microprocessor initiates a write to address 1046, allowing
the U16 output to go low, then high on the rising edge of WR. It should be noted that the U16
output is normally high and has no effect in clocking data to U20.
The microprocessor writes data to U20 on the four least significant bits of the
address/data bus.
The microprocessor establishes a high level on the AD3 line when BFO
frequency is to be displayed. The level, latched to the Q4 output of U20, is the FDP (Frequency
Decimal Point) output to the Front Panel Switchboard LED segment of the BFO frequency
display which illuminates to provide the decimal point.
The high FDP level ensures that the
decimal point illuminates during aU BFO frequency displays. The data on the remaining three
bits are latched to the Q1, Q2 and Q3 outputs to establish the switching characteristics of U14
(refer to paragraph 3.1.3.15). The levels on the three bits are determined by the operating
mode of the controller.
In local mode, the RF gain of the receiver (in manual gain mode) is established by
the front panel RF GAIN potentiometer. The microprocessor uses the LSB of the data bus to
establish the level at Q3 of U20 which controls the switching of the RF gain voltage (by U14) to
the VOLTAGE 2 output. VOLTAGE 1 is unused in this application.
The dual-purpose front panel meter indicates signal strength or audio level of the
receiver. When the front panel LINE AUDIO or SIGNAL STR switch is engaged, the processor
uses the AD1 and AD2 data bus bits to establish the levels at Ql and Q2 which control the
switching (by U14) of the appropriate voltage to the meter.
3.1.3.15
RF Gain/Meter Voltage Switch (UI4)
Switch U14 is a triple two-channel multiplexer having separate digital control
inputs (A, B, and C) and an inhibit input.
The inhibit line is tied to ground, holding the
multiplexer in an enabled state. Each control input operates one of a pair of channels which are
connected in a single-pole, double-throw configuration. The A input controls the X channels,
the B input controls the
Y
channels, and the C input controls the
Z
channels.
3-16
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