Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement page 109

CIRCUIT DESCRIPTION
WJ-8718A/MFP
3.4.1. 7.9
Transmitter Ready (Tx RDY)
The Tx RDY signal is raised high by the USART to inform the microprocessor that
the USART is ready to receive data from the microprocessor. The microprocessor interprets
the Tx RDY signal as an interrupt request, branches from the main program to a subroutine, and
executes the subroutine instructions. The Tx RDY signal automatically resets (goes low) when
the microprocessor writes data into the USART. Data written into the USART are automat-
ically transmitted via the USART as long as CTS is active (low).
3.4.1.7.10 Data Set Ready (DSR)
The
TISR
signal into the USART goes low when the remote controller is ready to
send data. The signal is applied to an active repeater network in each receiver under control.
Figure 3-12 illustrates the flow of a signal (
IJ'SR
or
CTS )
from the control equipment through
circuits representative of the repeater networks in three receivers. Additional receivers (up to
32) could be connected to the receiver chain in the· manner depicted in the illustration. The
logic levels illustrated are typical of an activated DSR signal; the opposite logic levels are the
steady state condition.
3.4.1. 7.11 Data Terminal Ready (DTR)
The DTR line from the USART goes low to inform the remote controller that the
VSART is ready to receive. This signal will go low only from the addressed receiver (or
receivers, if more than one receiver has the same address) and will be actively repeated by the
I/O boards in the receivers along the path to the controller. Figure 3-12 illustrates a typical
network of one controller and three receivers under control. The control signal into the
controller represents the DTR (or RTS) signal. Circuits shown are equivalent to the repeater
networks. In the figure, the logic levels on the receiver-to-controller lines are steady-state
conditions.
3.4.1. 7.12 Clear to Send (CTS)
A low logic level on the CTS input to VI tells the VSART that the controller is
ready to receive a transmission from the USART. The signal reaches the VSART through
circuits identical to the DSR signal path, described in paragraph 3.4.1.7.10. The USART will
not transmit data unless CTS is active (low).
3.4.1. 7.13 Request to Send (RTS)
A low logic level on the RTS output from the USART notifies the controller that
the USART is now. ready to
transmit.~e
signal reaches the controller through circuits
identical to the circuits discussed in the DTR signal description in paragraph 3.4.1.7.11.
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