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TABLE 2-3
Table 2-3. Receiver Address Codes (Cont'd)
WJ-8718A/MFP
Receiver Address
82-5
82-4
82-3
82-2
82-1
27
1
1
0
1
1
28
1
1
1
0
0
29
1
1
1
0
1
30
1
1
1
1
0
31
1
1
1
1
1
NOTE:
o
=
open, 1
=
closed
2.4.3
PREPARATION FOR IEEE STANDARD
488
OPERATION
Through the use of the WJ-8718/488M Option, up to 14 parallel-connected
receivers can be controlled by one controller. Before remote operation, each receiver must be
placed in the remote operating mode, and a valid receiver address must be established. Refer
to Figure 6-7, Type 796075 I/O Interface Schematic Diagram, when reading the following
inform a tion.
2.4.3.1
Remote Operating Mode
A receiver, designated as a listener, must be placed in the remote operating mode
by depressing the front panel REMOTE button or if the receiver has not previously been
commanded by a remote device, the first remote message received after power on will place
the receiver in a remote state.
The receiver can be addressed to talk regardless of the
REMOTE switch position.
The remote or local operating modes cannot be established by
remote command, but can be monitored.
2.4.3.2
Receiver Address
Parallel data from the controller is applied to all receivers under control, but only
the addressed receiver "recognizes" its address and accepts the data. The 5-bit address code is
established by switch settings in the 81 switch assembly on the I/O Interface (488-A3).
A
closed switch denotes a logic 1 and an open switch denotes a logic
o.
A valid receiver address
can be any binary-coded number in the 0 through 30 range, as listed in Table 2-3.
The logic levels established by the switch settings are inverted at the outputs of
tri-state buffer U4, and are loaded on the microprocessor bus lines when the processor
addresses U4 and initiates a read operation. The processor writes the receiver address into a
register internal to the microprocessor interface, 488-A3Ul, and, until Ul is reset, the
interface (488-A3U1) determines if the receiver address on incoming data is valid. The ability
of Ul to perform this service ensures that the microprocessor is interrupted only when a valid
data byte is waiting to be fetched, or a byte is needed for transmission.
2-4
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