Type 796056-1 Front Panel Encode (Mfp-Aial); Address Latch; Address Decoder (V19) - Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement

Microprocessor front panel option
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WJ-8718A/MFP
3.1.3
TYPE 796056-1 FRONT PANEL ENCODE (MFP-A1A1)
TABLE 3-1
Figure 6-3 is the schematic diagram for
the Front Panel Encode Board
(MFP-AIAl); Figure 3-1, Front Panel Section Block Diagram, shows the interdependent
relationship of all front panel boards.
The Front Panel Encode Board is powered by the following dc voltages: +5 Vdc
applied across the capacitive decoupling network formed by Cl through CI0 and C14 through
C16; -5 Vdc derived from -15 V at Jl pin 35 and the VRl, C17, and R19 voltage regulating
network; variable voltage derived from 10 V unregulated by Ul (paragraph 3.1.2.2.5) applied to
the 7-segment drivers at A60 and B25.
3.1.3.1
Address Latch (UI8)
Integrated circuit UI8 is an octal D-type flip-flop. TheCLR input is tied high,
allowing the, levels on the D inputs to transfer to the Q outputs on the positive-going edge of
the clock (CLK) input. During the time the clock input remains either high or low, changes in D
levels have no effect on the outputs.
The clock signal to U18 is the inverted (by UI3A)
microprocessor ALE control signal.
ALE transitions low when the microprocessor data bus
contains address data, latching the ADO through AD7 address bits to the U18 outputs. The ADO
bit is the AO input to the programmable keyboard/display interfaces (Ul and U2) and is
described in paragraphs 3.1.2.2.5 and 3.1.3.9.1.
The remaining lower-order address bits are
applied to address decoder U19, described in the following paragraph.
3.1.3.2
Address Decoder (UI9)
U19 decodes the address latched by U18 to provide enabling or clock inputs to all
addressable devices on the MFP-AIAI board. Table 3-1 is the U19 truth table. The YO through
Y3 outputs are normally high and go low only when the enabling and select inputs are as listed
in the table.
Table 3-1. U19 Truth Table
Inputs
Outputs
Enable
Select
Gl
G2A
G2B
C
B
A
YO
Yl
Y2
Y3
Y4
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
0
1
1
0
1
1
1
0
0
0
1
1
1
1
1
0
1
1
0
0
1
0
0
1
1
1
1
0
3-7

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