Control And Timing Sections; Return Line Circuits; Display Circuits - Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement

WJ-8718A/MFP
CIRCUIT DESCRIPTION
A high level on the AO lines indicates that the information transferred through the
data buffers is command or status, and a low level indicates data. When the interface is not
selected (CS
=
1) the buffers are in a high impedance state. The data buffers input during the
time WR and CS are low, and output when RD and CS are low. Refer to paragraphs 3.1.3.4.1
and 3.1.3.9.1 for information concerning the derivation of the CS, AO, RD, and WR signals.
3.1.3.3.2
Control and Timing Sections
The internal control and timing registers store mode and operating conditions
programmed by the microprocessor. Conditions are programmed by commands on the data lines
when AO is high and WR is low. The command word is latched into the interface when WR
transitions to high, and the interface circuits decode and execute the command.
The timing circuits receive an external CLK signal generated by the external
network of U13E and F, R7, and Cll. The time constant of R7 and Cll, in conjunction with the
feedback and inversion. characteristics of U13E and F, provides square wave pulses of 1 MHz.
Internal counters divide the reference frequency as required, to synchronize internal timing
with the programmed microprocessor cycle time.
The RESET input is set high, resetting the interface circuits, when the micro-
processor completes its reset procedure following power-up.
The scan counter provides a 4-bit binary count to the SLO through SL7 output lines.
An external decoder drives the keyboard scan lines, and an external demultiplexer switches the
BCD code levels on the BO through B3 pins to provide inputs to LED cathode drivers.
3.1.3.3.3 Return Line Circuits
The return line circuits include buffers, keyboard debounce and control circuits,
and an 8 x 8 FIFO/Sensor RAM. The RLO through RL7 lines are connected to the column scan
lines through closed front panel switches. The return line circuits 'scan the lines, detect a
closed switch, code the switch position, and store the code in the 8 x 8 FIFO/Sensor RAM. The
microprocessor accesses the RAM locations to read the status of the switches (under program
control).
3.1.3.3.4
Display Circuits
The display section includes registers which establish the levels on the BO through
B3 output lines. These lines are synchronized with the scan lines to provide a BCD output to an
external decoder/driver which drives the front panel LED and display segment anodes. The
interface automatically refreshes the displays.
Other display circuits are address registers and a 16 x 8 RAM. The microprocessor'
configures the display characteristics through the use of the display RAM. In this MFP
application, the RF frequency display is configured for right or "calculator style" entry. The
first numerical front panel keypad entry (for RF frequency, threshold level, dwell time, or
memory address) is placed in the right most display character and is shifted left one character
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