Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement page 89

CIRCUIT DESCRIPTION WJ-8718A/MFP
3.2.4.8
Freguency Registers (U12-U17)
U12 through U17 are octal D-type flip-flops and are identical to the U5 and U6
latches described previously, except they are standard CMOS parts. These registers serve as
latches for the receiver LO synthesizer and BFO synthesizer circuit.
The clock input to each register is tied to one of the Y outputs of decoder U8.
When a hexadecimal address between 1030 and 1035 is on the data bus and a write cycle is
executed, one of the Y outputs goes low for the duration of the inverted write input on Gl.
This positive-going edge of the Y output causes its data on the bus to be clocked from the D
input to the Q output. These signals are then used by the necessary inputs to its LO and BFO
circuits.
3.2.5 TYPE 794308-2 IF INTERFACE (MFP-A3)
The IF Interface Board replaces the Front Panel Interconnect (A6A2) in the
WJ -8718A HF Receiver. The board provides signals that control appropriate devices in the IF
section of the receiver. These functions include gain mode, bandwidth, detection mode, RF
gain control, AGC dump, sideband audio switching, audio squelch, signal strength monitoring,
synthesizer tuning voltages,
±
15
V,
and audio outputs.
The IF Interface Board also provides circuitry for interfacing to a standard front
panel WJ-8718A HF Receiver. These circuits are omitted for use when installed in a MFP
equipped receiver; therefore, the Type 794308-1 IF Interface Board, which contains these
circuits, is not covered in this discussion.
Figure 3-10 is a simplified block diagram and Figure
6-5
is the schematic diagram
for the MFP-A3 board.
3.2.5.1
Bidirectional Bus Transceiver (U20)
Transceiver U20 is made up of 16 high speed CMOS buffer devices. Only eight
buffers are enabled at one time. The direction, or the specific buffers that are enabled, is
controlled by the DIR input at pin 1. The pin 1 input is connected to the RD line through U13B
and U19A for any address decode of 101X (through U10D) or 103X (through U10A). Refer to
Table 3-13 for additional 101X addressing information. (Besides decoding, the 103X is used for
devices on the Type 794308-1 Board for a standard receiver, and is therefore not mentioned
again in this description.)
When the RD is active for one of the decoded addresses, the buffers are enabled to
allow data to be transferred from the board to the external circuits. In all other cases, these
buffers are disabled and their opposites are enabled to allow data transfer from the external
circuit to the board.
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