Table of Contents
Advertisement
TABLE 3-5
3.1.3.8
Table 3-5. U4
Truth
Table
A
B
C
D
INH
Selected Channel
X
X
X
X
1
None
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
2
1
1
0
0
0
3
0
0
i
0
0
4
1
0
1
0
0
5
0
1
1
0
0
6
1
1
1
0
0
7
0
0
0
1
0
8
1
0
0
1
0
9
0
1
0
1
0
10
1
1
0
1
0
11
0
0
1
1
0
12
1
0
1
1
0
13
0
1
1
1
0
14
1
1
1
1
0
15
Display Driver (U3)
WJ-8718A/MFP
LED driver
V3
decodes the BCD code at the A, B, C, and D inputs to provide a high
output level to the segments associated with the selected digit, forward biasing the segment
anodes and causing display of the digit.
The outputs of
V3
also drive the LED indicators
associated with Group 1: the tuning resolution, LOCK pushbutton, and fault lights.
3.1.3.9
Group 2 Interface
(V2)
The
V2
interface scans the front panel switch matrix defined as Group 2 and
interfaces the associated LED indicators and displays.
Refer to paragraph 3.1.2.2.2 for a
discussion of the switch matrix.
3.1.3.9.1
U2 Control Inputs (CS,
AD,
WR, RD)
The
V2
interface is addressed by the microprocessor data bus at hexadecimal 1044
or 1045. The address is latched by V18 when the ALE signal goes low, U19 is enabled and the
CS signal (the Y2 output of V19) goes low to enable V2. The level on the AO input to VI is
established by the LSB of the address. The microprocessor uses address 1044 (LSB
=
0) if the
information to be transferred on the data bus is to be interpreted (by
U2)
as data. The address
1045 (LSB
=
1) is used if the data bus word is to be interpreted as command status. The WR
signal goes low to permit the microprocessor to load the bus with a word to be transmitted to
VI; the word is latched into U2 when WR transitions high. The microprocessor sets RD low to
request information from U2.
TheV2
data buffers load the information on the data bus when
RD is low, and when RD transitions high, the information is latched by the microprocessor.
3-14
Advertisement
Chapters
Table of Contents
