Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement page 84

Microprocessor front panel option
Hide thumbs Also See for WJ-8718A/MFP:
Table of Contents

Advertisement

WJ-8718A/MFP
Table 3-7. RAM/EPROM Address Data
TABLE 3-7
3.2.4.3.2
Address bit
2 3 -2 0
2 3 -2 0
2 3 -2 0
2 3 -2 0
Address Line
15-12
11-8
7-4
3.,.0
EPROM 1
From 0000
-
0000
0000
0000
0000
To OFFF
-
0000
1111
1111
1111
EPROM 2
From 4000
-
0100
0000
0000
0000
To 4FFF
-
0100
1111
1111
1111
RAM
From 2000
-
0010
0000
0000
0000
To 27FF
-
0010
0111
1111
1111
Control Inputs
The CE inputs to U1 and U2 are chip-select pulses from de-eode circuit U7. The
low enable pulse to U1 is provided when decoder U7 senses that the hexadecimal-coded address
on the microprocessor data bus is in the range of 0000 through OFFF; the low enable pulse to U2
is provided when the hexadecimal address is in the range of 4000 through 4FFF.
The
microprocessor addresses location 0000 at power-up and consecutively reads and executes the
instructions stored in EPROM.
The OE inputs are tied to the microprocessor RD signal, which is pulled low when
the processor initiates a read operation. Output Enable (OE) is used to take the outputs out of
tri-state.
3.2.4.3.3
Read Mode
When the microprocessor initiates
a
read operation, the 16-bit memory address is
placed on the data bus, ALE goes low, and if the memory addressed is RAM or EPROM, U7 is
enabled. If the hexadecimal coded address is between 0000 and OFFF, U7 pulls the UI Chip
Enable (CE) line low, and the ADO through AD7 address bits (from low-order address latch U5)
and the AS, A9, AIO, and All address bits are applied to the EPROM device through Address
Inputs AD
throu~
All.
After an address access time, followed by the falling edge of the
microprocessor RD signal, the data stored in the addressed memory location are available at
the 00 through 07 EPROM Data Outputs. In the same manner, if the hexadecimal address is
between 4000 and 4FFF, U7 enables EPROM U2.
The data are loaded on the ADO through AD7 address/data bus lines and latched
into the microprocessor's internal instruction register (paragraph 3.2.3.1.2), on the rising edge
of RD.
3-29

Advertisement

Table of Contents
loading

Table of Contents