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TABLE 3-25
Table 3-25. Addresses 1020, 1021, and 1022
WJ-8718A/MFP
Address Bit
2 3 22 2 1 2 0
2 3 22 2 1 2 0
2 3 2
2
2
1
2 0
2 3 22 2 1 2 0
Data Line
15 14 13 12
11
10
9
8
7
6
5
4
3
2
1
o .
Ul
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
Ul
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
U3
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
NOTE:
Data Lines 0-7
=
ADO - AD7
Data Lines 8-15
=
A8 - A15
3.4.1.2.2
U4 Select
The select inputs to U4 at A, B, and C are the address bits carried on the ADl,
AD2, and AD3 data lines. (Note that the least significant bit of the address, carried on ADO is
not a decoder input. This bit has a unique use and is discussed in paragraph 3.4.1.7.5.
Two of the eight available outputs of U4 are used to enable the two addressable
devices (UI and U3) on the I/O board. Comparison of Tables 3-24 and 3-25 shows that the YO
output goes low when one of the two UI addresses is latched by U2, and YI goes low when the
U3 address is latched.
3.4.1.3
Switch Assembly (S2)
The eight-position switch assembly (82) is used, prior to remote operation, to
establish a receiver address for receiver master/slave configuration, and to enable parity check.
If
parity is enabled, the switch establishes odd or even parity.
Table 2-2 lists the switch
functions. A high logic level indicates a closed switch and a low logic level indicates an open
switch.
.
Paragraph 2.4.2.3, part of the preparation for operation procedure, contains a
description of the switch settings.
3.4.1.4
Tri-State Buffer/Inverter (U3)
Octal tri-state buffer U3 allows the microprocessor to read the settings of the S2
switch assembly. The buffer inputs the logic levels of the switch settings from the pun-up
resistive network, Ul1. The outputs of U3 are tri-stated if the logic levels at the enable inputs
(pins 1 and 19) are high. When the enable inputs go low, the outputs of U3 are taken out of tri-
state and the data from the 82 switch assembly are inverted and placed on the lower-order
address/data bus lines. U3 is enabled when the RD signal from the microprocessor goes low
(after the address is latched) and when U4YI is low. As discussed in paragraph 3.4.1.2.2 U4Yl
is low only when address 1022 is latched by U2.
3-50
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