Operation; Data Lines; Connector Pin Assignments - Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement

WJ-8718A/MFP
TABLE 2-18
2.4.5.3 488M Operation
The IEEE Standard 488-1975 Interface Bus is organized into three sets of signal
lines: eight bidirectional data lines, three handshake lines, and five management control lines.
The interface point between the bus and the receiver under control is a 24-pin Amphenol
receptacle mounted in the rear panel of the receiver at the REMOTE INPUT. Table 2-18 lists
the 488 connector pin numbers with the respective interface signals and functions. Figure 2-6
illustrates the bus structure.
Table 2-18. 488 Connector Pin Assignments
Pin Number Signal
Description
1-4 DIOI-4
Data Input/Output Lines
13-16
DI05-8
Data Input/Output Lines
5 EOI End or Identify
6 DAV
Data Valid
7 NRFD Not Ready For Data
8
NDAC Not Data Accepted
9 IFC Interface Clear
10 SRQ Service Request
11 ATN Attention
12 SHIELD
Shield
17
REN Remote Enable
18-23
GND Ground
24 GND, LOGIC Logic Ground
2.4.5.3.1 Data Lines
A set of eight data input/output lines, DI01 through DI08, carries all addr-ess and
parameter data from the receiver rear panel REMOTE INPUT through 488-A3Jl to non-
inverting transceivers U2 and U3. A bit-parallel, byte--serial, negative logic form is used for
the bidirectional transfer of data, received in one of two data modes dependent on the level of
the ATN management line.
When the ATN line is low, data received is read as receiver address data which
place the receiver in the listen, or talk, state. An unlisten data word can also be sent by the
controller that unaddresses all previously addressed devices, allowing the devices to accept data
when the DAV line is active (low) and the ATN line is high. Equipment address codes
(Table 2-3) can be converted to standard ASCII (American National Standard Code for
Information Interchange) characters. The address code is an 8-bit binary-coded word reflecting
the levels established by the 488-A3S1 settings (paragraph 2.4.3.2) in the five least significant
bits. The format of data transfers on the DIO lines is discussed in greater detail in
paragraph 2.4. . . 5.4.
2-23