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WJ-8718A/MFP
CIRCUIT DESCRIPTION
A low level on a control input connects the related XO, YO, or ZO line to the X, Y
or Z channel; a high level on a control input connects the related Xl, Yl, or Zlline to the X, Y,
or Z channel. For example:
A
=
1,
A = 0,
B = 1,
B
=
0,
C
=
1,
C
=
0,
x
= Xl
X
=
XO
Y = Y1
Y
=
YO
Z
=
Zl
Z
=
ZO
The processor establishes the levels on the select inputs through data latch U20,
described in pa.ragraph 3.1.3.14.
The C input to U14 switches the variable RF gain voltage
(RFG) at Z to the VOLTAGE 2 output from ZOo The
A
input switches the signal strength
(88)
voltage to the YO channel where the
B
input selects either the signal strength or audio level
voltage to be sent through YO to the front panel meter (from XAIA pin A33).
3.1.3.16
Tuning Wheel Register (U17)
Integrated circuit U17 is a 4-bit D-Type flip-flop register with tri-state outputs.
Two of the flip-flops are used in this application. The flip-flop outputs, Ql and Q2, tell the
microprocessor if the front panel tuning wheel is being rotated and, if so, in which direction:
clockwise to increase the displayed frequency (at the selected step size) or counterclockwise to
decrease the frequency.
Table 3-6 is the U17 truth table. The table shows that the levels at the D inputs
transfer to the
Q
outputs on the positive-going transition of the clock pulse when G 1, G2, and
clear (CLR) are low; in addition, the Q outputs must be enabled by low levels on the ODI and
OD2 inputs. A high level on the clear input resets the flip-flops and all Q outputs -go low.
The low levels required to allow data at the D inputs to be clocked to the
Q
outputs
are provided as follows:
1.
Gl and G2 are tied to ground.
2.
OD1 is low (through AND gate UI5C) when RD is low.
3.
·OD2 is low when
U19YO goes low
or, as explained in
paragraph 3.1.3.2, when the hexadecimal address 1040 has been
on the microprocessor address/data bus and latched by U18.
4.
Clear is the inverted level onU19Yl (by UI5D). When U17 is
addressed, only one of the U19 outputs (YO) is low, all others
are high; therefore, clear is low when U17 is addressed by the
microprocessor.
When clear goes high, the
Q
outputs of U17
are reset. The processor resets U17 by a RD to address 1048.
3-17
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