Watkins-Johnson Company WJ-8718A/MFP Instruction Supplement page 106

WJ-8718A/MFP
TABLE 3-26
The microprocessor initiates a read operation to address 1022 (U3) to determine if
the equipment address on incoming data is valid.
3.4.1.5 Baud Rate Network (U5, 51)
Baud rate is established by entering a baud rate select code in the four-position
switch assembly, Sl, described in paragraph 2.4.2.2. Baud rate generator US is an N-Channel
LSI device capable of generating 16 selected frequencies (see Table 2-1) from a single input
frequency.
The baud rate generator is basically a programmable IS-stage feedback shift
register capable of dividing any module up to 2 15 less 1 (32,767).
The device is driven by
external crystal Y1 with a resonating frequency of 5.0688 MHz. Pin functions are listed in
Table 3-26.
Table 3-26. Baud Rate Generator Pin Functions
Pin No. Symbol Name Function
1 Xl Crystal input 1 One pin of Y1
2 X2 Crystal input
2
One pin of Y1
3 VCC Power supply +5 Vdc
5
GND Ground
Common return
8
FO Reference frequency Reference output at
1/4 F IN
9 STB Strobe
A hi.gh logic level loads
inputs A, B, C, and
D
into US.
10-13
D,C,B,A Input address Logic levels select
F OUT.
14 F OUT Output frequency
Frequency selected by
input address.
3.4.1.6 Active Repeater Network
The Jl and J2 connections on the I/O board allow up to 32 receivers to be joined in
a daisy chain and placed under control of one RS-232 compatible .controller. Jl connects to the
rear panel REMOTE INPUT and J2 connects to the rear panel MONITOR OUTPUT. In the daisy
chain configuration, the monitor output of a receiver is connected to the REMOTE INPUT of
the next receiver in the chain (see Figure 2-2). The remote control equipment connects to the
REMOTE INPUT of the first receiver in the chain.
Signal and data transmissions are applied to each unit in the chain and are ac.cepted
by the addressed unit or units. Each I/O board actively repeats the transmissions, in both
directions, assuring signal integrity.
Each handshake signal (RTS, DTR, DSR, and CTS) and each data bit (Rx and Tx
data) passes through a repeater network consisting of a NAND gate circuit. The function of
each line and the repeater network logic is discussed in the description of USART, U1
(paragraph 3.4.1.7).
3-51