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Table 1-4: DDR3 SODIMM Socket J1 Connections to the FPGA (Cont'd)
Table 1-5: DDR3 SODIMM Socket J3 Connections to the FPGA
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
XCVX690T (U1) Pin
E19
F19
G19
K19
J18
E20
F20
K17
H20
H18
J17
J20
P18
G17
DDR3_A_TEMP_EVENT_B
XCVX690T (U1) Pin
AN19
AR19
AP20
AP17
AP18
AJ18
AN16
AM16
AK18
AK19
AM17
AM18
AL17
AK17
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Net Name
DDR3_A_CLK0_P
DDR3_A_CLK1_N
DDR3_A_CLK1_P
DDR3_A_CKE0
DDR3_A_CKE1
DDR3_A_RAS_B
DDR3_A_WE_B
DDR3_A_CAS_B
DDR3_A_ODT0
DDR3_A_ODT1
DDR3_A_S0_B
DDR3_A_S1_B
DDR3_A_RESET_B
Net Name
DDR3_B_A0
DDR3_B_A1
DDR3_B_A2
DDR3_B_A3
DDR3_B_A4
DDR3_B_A5
DDR3_B_A6
DDR3_B_A7
DDR3_B_A8
DDR3_B_A9
DDR3_B_A10
DDR3_B_A11
DDR3_B_A12
DDR3_B_A13
Feature Descriptions
SODIMM Memory J3
Pin Number
Pin Number
101
CK0_P
104
CK1_N
102
CK1_P
73
CKE0
74
CKE1
110
RAS_B
113
WE_B
115
CAS_B
116
ODT0
120
ODT1
114
S0_B
121
S1_B
30
RESET_B
198
EVENT_B
SODIMM Memory J3
Pin Number
Pin Name
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12_BC_N
119
A13
15
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